I used Chipscope inserter in my design and found sometimes it's hard to find the net I am interested in the netlist.
The synthesizer may change the signal's name.
Is there any way to prevent this happen?
I tried using synthesis constraints in my hdl,but some signals were also missing.
And,I found when connected the probe points to signals driving output pins,the translator will report an error like
"bidirect pad net 'dout<6>' is driving non-buffer primitives:"
What should I do?Thanks!
Try few things.
1. Always select "Keep Hierarchy".
2. Syntheis will do optimization on your logics hence sometime removes unused flops/signals...You may have to use the signal to feed some dummy logic so that synthesis willn't optimize/ remove it.
hope it helps.