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Scholar ronnywebers
Scholar
6,764 Views
Registered: ‎10-10-2014

after 'setup debug', do I need to run synthesis again?

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Vivado 2015.4



  • I've marked some nets in my Zynq bd for debug
  • then I launch synthesis
  • upon completion I launch 'setup debug'
  • when I complete the setup debug dialog, they synthesized design shows an 'asterix' (*), to indicate that it has been modified.
  • Then I cllose the synthesized design, upon which it asks to save the modifications
  • I answer 'yes' -> it adds constraints for the new ILA to the target .xdc file
  • When done, the upper right corner of Vivado says 'synthesis complete'

 

Q : Can i just click 'run implementation' (or even 'generate bitstream') from this point, or do I need to run synthesis again to 'incorporate' the new constraints concerning the created ILA?  Or is the ILA not handled by the synthesis engine, and is it a task for the implementation engini?

 

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Moderator
Moderator
12,449 Views
Registered: ‎07-01-2015

Re: after 'setup debug', do I need to run synthesis again?

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Hi @ronnywebers,

 

I agree to recommendations given in UG.

When you are using setup debug then tool will mark as synthesis complete even though the constraints are added to XDC. Say you are writing constraints to XDC regarding ILA then tool will take it as general constraints editing. In such scenario synthesis will go out of date then you can use force-up-date in such case.  

 

If you see the UG recommendation answers the pop-up which comes while saving the ILA constraints.

 

Conclusion- After adding ILA using setup debug you can straight away run implementation without resynthesizing the design. In order to verify if the ILA is inserted in netlist or not you can close and reopen the schematic and you will see ILA in netlist. 

Thanks,
Arpan
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8 Replies
Scholar u4223374
Scholar
6,760 Views
Registered: ‎04-26-2015

Re: after 'setup debug', do I need to run synthesis again?

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I've always just run implementation from that point, and it's always worked fine.

Community Manager
Community Manager
6,754 Views
Registered: ‎07-23-2012

Re: after 'setup debug', do I need to run synthesis again?

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The tool suggests to re-run the synthesis as the xdc was modified. You need not re-run the synthesis.
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Xilinx Employee
Xilinx Employee
6,749 Views
Registered: ‎02-14-2014

Re: after 'setup debug', do I need to run synthesis again?

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Hello, Check the note on page #102 from this UG http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug908-vivado-programming-debugging.pdf
Regards,
Ashish
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Moderator
Moderator
6,748 Views
Registered: ‎07-01-2015

Re: after 'setup debug', do I need to run synthesis again?

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Hi @ronnywebers,

 

After saving the XDC file after inserting ILA no need to run synthesis again. You will get a pop-up similar to attached snapshot. You can close the synthesized design and open it again you will see the ILA inserted to the netlist. Generally synthesis won't go out of data after inserting ILA. In case it goes you can use Force up to date for synthesis.

Thanks,
Arpan
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Scholar ronnywebers
Scholar
6,739 Views
Registered: ‎10-10-2014

Re: after 'setup debug', do I need to run synthesis again?

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thanks all, 

 

@arpansur : I've checked the UG p 102 that @ashishd mentioned, and that says :

 

IMPORTANT: Saving constraints to the target constraints file while in project mode may cause the
synthesis and implementation steps to go out-of-date. However, you do not need to re-synthesize the
design since the debug XDC constraints are only used during implementation. 

however in your your answer @arpansur you wrote 'generally' ... so is there any exception thinkable to the quote from the UG above?

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Scholar pratham
Scholar
6,729 Views
Registered: ‎06-05-2013

Re: after 'setup debug', do I need to run synthesis again?

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@ronnywebers In any case you don't have to re-run synthesis again. Just force up-to date and tool would take care always.

-Pratham

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Moderator
Moderator
12,450 Views
Registered: ‎07-01-2015

Re: after 'setup debug', do I need to run synthesis again?

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Hi @ronnywebers,

 

I agree to recommendations given in UG.

When you are using setup debug then tool will mark as synthesis complete even though the constraints are added to XDC. Say you are writing constraints to XDC regarding ILA then tool will take it as general constraints editing. In such scenario synthesis will go out of date then you can use force-up-date in such case.  

 

If you see the UG recommendation answers the pop-up which comes while saving the ILA constraints.

 

Conclusion- After adding ILA using setup debug you can straight away run implementation without resynthesizing the design. In order to verify if the ILA is inserted in netlist or not you can close and reopen the schematic and you will see ILA in netlist. 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

Moderator
Moderator
6,674 Views
Registered: ‎07-01-2015

Re: after 'setup debug', do I need to run synthesis again?

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Hi @ronnywebers,

 

Is your query addressed?

If so please close this thread by marking the appropriate answer as solution in the interest of other users.

Thanks,
Arpan
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