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Explorer
Explorer
6,556 Views
Registered: ‎08-28-2008

an example shows, how difficult to manage the design in Vivado IP integrator is

i record a GIF (the attchment file) to show the Vivado IP integrator tools is the most difficult to manage one i've used!!

the bus port fold automatically, i have to unfold it time to time.

the block changes its location every time, i have to relocate it time to time

the nets are in chaos, which are not better than the spider net. you can never manual route the net, you just accept it.

the port of the blocks is fixed and can never be reorder.

 

in all, it is the worst GUI tools i've use to manage the HDL design,

do you ever use it to finishes a REAL design with the tool? do you really enjoy repeat unnecessary mouse clicking?

there are many perfect HDL GUI tools, such as Mentor HDL designer, if you borrow little function from it, the IP integrator is more easy to use

 

 

inintergtation.gif
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Explorer
Explorer
6,555 Views
Registered: ‎08-28-2008

i spend minutes to setup a Miceoblaze system in EDK; however, i spend hours to setup the Miceoblaze system in Vivado IP integrator, and more i am worry about the SpiderNet-like nets wire are all correctly or NOT!!!

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Xilinx Employee
Xilinx Employee
6,520 Views
Registered: ‎08-21-2007

Thank you for the post.  We see the problem with the screen moving around and will fix it.  That is a bug.  The screen should be stable.

 

I would like to understand why you are connecting each signal one at a time.  Why are you not connecting the entire S02 interface all at once and allowing IP Integrator to do the work of connecting each signal for you?  The S00 and S01 interfaces are connected with a single connection.  Thanks!

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Explorer
Explorer
6,461 Views
Registered: ‎08-28-2008

hi Timv

my microblaze is a subsystem in the FPGA, it is synthesized alone with other blocks.

S00 & S01 are connected to Miceoblazes

S02,& S03 are external AXI Master Ports

 

for the AXI external interface, some of the signals are constant, i would like to connect it to a constant internally, so the synthesizer could optimize it.

 

and i do not want to change any of the automatical generating  HDL wrapper, as the block design may be change, i do not want to change HDL wrapper each time for a new generated wrapper.

 

i understand if i leave it outside, the placer or router also could optimize them, but i think the synthesizer would be optimize better in RTL level...or if i am wrong.....

BTW, the each signal connecting cannot be saved in IPI

thanks for your reply, hoeping the tools get better in next release

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