08-04-2020 09:09 PM
I'm using axi protocol checker to debug my system, basically mount it inside a block design to the axi interface of ddr ip.
then instantiate this block design inside verilog files.
the enable mark_debug switch is set to yes.
1. The xdc generated in IP source did have mark_debug set for the pc_status pins
set_property mark_debug true [get_nets pc_status* ]
2. The instantiated .sv file also set the mark_debug by:
But after synthesis, there is no mark debug in the netlist signals. seems still need to manually add mark_debug for the signals.
I don't know if this mark_debug is not like the ones marked in verilog or I'm not doing it correctly. when adding debug core, the signals are also not there.
( Vivado 2019.1 on Ubuntu 18.04.2 LTS )