We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor jasper298
Registered: ‎05-08-2018

behaviour only as expected with ILA core

Hi all,


I have a design with a 8 channel ADC. The ADC is communicating with SPI. In a FSM the ADC data is read (16 bit), upper 3 bits are the channel ID and depending on the upper 3 bits, I put them in the corresponding register which is read via AXI.

via the UART, I have communication to read the ADC data from each channel but channel 0 will never update. ONLY when I place a MARK DEBUG attribute on the signal and check with the hardware manager, I see the signal is updating. How is that possible?


0 Kudos
1 Reply
Registered: ‎02-09-2017

Re: behaviour only as expected with ILA core

Hi @jasper298,


So just to confirm my understanding, are you checking the registers via AXI and they are not updating?


When you add the ILA, do you see the correct updated info in the ILA waveform and also in the AXI transaction, or just in the ILA?


Are you using a JTAG to AXI IP for such communication?


Could you share some screenshots and code so we can better understand the issue?


The ILA goes inside the logic, before it reaches any I/O port, so I initially suspect that it might be some XDC constraint that is not working. It could also be that the AXI transactions are not working for some reason.



Andre Guerrero

Product Applications Engineer

Don’t forget to reply, kudo, and accept as solution.
0 Kudos