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Registered: ‎02-11-2019

bitstream error

Hello..

I am using xilinx vivado 2016.3 with MYC-Y7Z020 zynq SOM . i am getting bitstream generation error like below .

  • Implementation
  • Write Bitstream
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.
  • [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

 

Can you please help me with this ?

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anunesgu
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398 Views
Registered: ‎02-09-2017

Hi tnareshnaresh7@gmail.com ,

 

Please take a look at https://www.xilinx.com/support/answers/59774.html

In addition, I found the following information:

This Error happens when IO and related IO components are placed in a Reconfigurable Module.
The UG909 lists the type of logic that can and can not be placed in a RM module.

Logic that must remain in the static logic:

  • Clocks and Clock Modifying Logic - Includes BUFG, BUFR, MMCM, PLL, and similar
  • I/O and I/O related components (ISERDES, OSERDES, IDELAYCTRL, etc.)
  • Serial transceivers (MGTs) and related components
  • Individual architecture feature components (such as BSCAN, STARTUP, XADC, etc.)

So if IODELAY components are placed in a RM area, then the tool is not able to replicate the IODELAYCTRL associated and will fail with the above message.

Thanks,

Andre Guerrero

Product Applications Engineer

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368 Views
Registered: ‎02-11-2019

Hello ..
i follow the samw what they mention in that post? still i am getting this error
[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

[DRC 23-20] Rule violation (PLIDC-8) IDELAYCTRL missing for IODELAY - The IODELAY cell 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd' has no associated IDELAYCTRL. IDELAYCTRL cell is required to calibrate IODELAY cells.

 

My constraints are below please find that.
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl]
set_property LOC IDELAYCTRL_X1Y1[get_cells time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd]
set_property LOC IDELAYCTRL_X1Y1 [get_cells time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd]

My clock region in X1Y1

i am getting constrainst warring like below:
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl', Could not legally place instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl at IDELAYCTRL_X1Y2 since it belongs to a shape containing instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i. The shape requires relative placement between time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx_ctl and time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rgmii_rx_ctl_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":166]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd', Could not legally place instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[0].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd and time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[0].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[0].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":167]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd', Could not legally place instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[2].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd and time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[2].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[2].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":169]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd', Could not legally place instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[3].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[3].delay_rgmii_rxd and time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[3].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[3].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":175]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd', Could not legally place instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[2].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[2].delay_rgmii_rxd and time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[2].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[2].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":174]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd', Could not legally place instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[0].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[0].delay_rgmii_rxd and time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[0].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[0].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":172]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl', Could not legally place instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/rgmii_rx_ctl_ibuf_i. The shape requires relative placement between time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.delay_rgmii_rx_ctl and time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/rgmii_rx_ctl_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/rgmii_rx_ctl_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":171]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd', Could not legally place instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[1].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd and time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[1].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[1].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":168]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd', Could not legally place instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd and time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":170]
[Vivado 12-2285] Cannot set LOC property of instance 'time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd', Could not legally place instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd at IDELAYCTRL_X1Y1 since it belongs to a shape containing instance time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[1].rgmii_rxd_ibuf_i. The shape requires relative placement between time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/time_sync_gmii_to_rgmii_0_0_core/i_gmii_to_rgmii/i_gmii_to_rgmii/gen_rgmii_rx_zq.rxdata_bus[1].delay_rgmii_rxd and time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[1].rgmii_rxd_ibuf_i that can not be honoured because it would result in an invalid location for time_sync_i/gmii_to_rgmii_0/U0/i_gmii_to_rgmii_block/ibuf_data[1].rgmii_rxd_ibuf_i. ["E:/precision_timesyncxc7z20/time_sync/time_sync.srcs/constrs_2/new/constraints.xdc":173]
how to resolve this type of errors ?

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