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Explorer
Explorer
18,448 Views
Registered: ‎08-23-2011

chipscope triggers and data collection setup ...

hi,

 

i was trying to debug my fpga design using chipscope and i was wondering if i could do the following -

 

i want to collect data only on the rising edge of data_valid. then wait till the data_valid goes to 0 and then on the next rising edge collect another data value. the data_valid signal is synchronous but not periodic. and if i set my chipscope to capture 1024 samples, then i want it to capture 1024 data values on every rising edge of the data_valid signal. so the collection should be triggered on the 1st rising edge of the data_valid signal but then the next sample should be collected only on the next rising edge of the data_valid. is this possible in chipscope?

 

also, in the clock for chipscope, can i set a non periodic signal as the clock? for eg - if i set my data_valid as clock, and i set chipsope to - "sample every rising edge", then it might solve the above problem. is this possible in chipscope?

 

please advice ...

 

thanks and regards,

z.

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Professor
Professor
18,446 Views
Registered: ‎08-14-2007

Re: chipscope triggers and data collection setup ...

In Chipscope, when you configure the ILA you have the option for different trigger modes.  If

you choose "Basic trigger with edges" then you can set a trigger to use the rising edge of

a signal (as well as high or low levels or falling edge).  I would suggest having at least

two match units and using one as the storage qualifier (you also need to enable this

when you configure the ILA).

 

Otherwise there is no reason that the clock needs to be periodic, but it would help to use

a signal that is globally buffered.  ChipScope also doesn't let you look a a partially filled

buffer, so if you ask for 1024 samples you have to wait for at least 1024 qualified edges

before you can view the collected waveforms.

 

Finally, because you have access to the logic in your FPGA, you can create signals that

perfom unusual trigger operations to meet your specific needs and use those signals

for storage qualification and/or triggering.  I have often added counters and state logic

to help debug errors that are not easy to figure out the source.  For example I had a

state machine that got hung up in a particular state.  So I added a counter to trigger when

the state machine stayed in that state at least 256 cycles, and set my trigger position

so I could see the previous 512 cycles to find out how the machine got into that condition.

 

-- Gabor

-- Gabor
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Explorer
Explorer
18,432 Views
Registered: ‎08-23-2011

Re: chipscope triggers and data collection setup ...

hi gabor, 

 

thanks for your reply. i am new to chipscope so im having some issues in setting even the simplest trigger. i have an FPGA board which is using a differential clock going into ibufgds. from there, the o/p is routed to bufg which i then use for clocking my FPGA. 

 

then i select 2 triggers - the clock (set as basic) and a counter data (set as basic as well). however, when i load the bit file. in the trigger setup, i set the clock trigger to 1 and dontcares for the counter data, sampling at every rising edge of clock, but when i run chipscope, i get a message - "waiting for upload" ... nothing happens. when i trigger immediate, i just get 1 sample on the waveform.

 

i am wondering if there is some limitation where ibufgds portmapped to bufg clock wont work for chipscope?

 

do let me know ...

 

thanks and regards,

z.

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Professor
Professor
18,427 Views
Registered: ‎08-14-2007

Re: chipscope triggers and data collection setup ...

I think you're missing a piece of the ChipScope concept.  ChipScope is a fully synchronous

logic analyser using a single clock input which represents the maximum data collection rate

(sampling rate).  You should connect the clock input of ChipScope to the global clock of your

design.  Do not connect the global clock signal to a trigger or data input pin of Chipscope.

 

ChipScope conditional storage uses a match unit to generate a clock enable (synchronous

to the same global clock) for storing data in the buffer.  In the match unit, a "rising edge"

is defined as an input being sampled as 0 on one clock and 1 on the next clock.  This

is not the same as the clock input of a flip-flop.  If you use the rising edge match condition

for storage, you should see the data from the same cycles where the edge-event

signal was first sampled high.

 

-- Gabor

-- Gabor
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Explorer
Explorer
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Registered: ‎08-23-2011

Re: chipscope triggers and data collection setup ...

hi gabor,

 

ya ... i was mapping the clk to trigger/data pin of the chipscope so i guess i was having a problem. i do get the couter properly but now i want to see the values w.r.t the clock. 

 

i tried mapping the clock to some internal signals / output ports. but the when i go to make the connections in chipscope, i cant see the original clock signal. i only can see the port / internal signal i assigned the clock to ... for eg -

 

to clarify - i used the process below to reflect the 100 MHz new_clk_100 to the o/p port - port_clk_100

 

--process to detect 100MHz clk for chipscope
process (new_clk_100)
begin

if (new_clk_100 = '1') then
port_clk_100 <= '1';
else
port_clk_100 <= '0';
end if;

end process;

 

but in chipscope assignments, i dont see new_clk_100 anymore. i can just see port_clk_100. so how can i see the signals w.r.t the clock. ? i need to do this in order to detect race conditions on my FPGA. any way around it?

 

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Explorer
Explorer
18,424 Views
Registered: ‎08-23-2011

Re: chipscope triggers and data collection setup ...

just to clarify - i want to see my clock and the counter values in the waveforms. so that i can see the rising edge of the clock and the data values at that time and check for any race conditions? any way of doing that?

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Professor
Professor
18,412 Views
Registered: ‎08-14-2007

Re: chipscope triggers and data collection setup ...


@zubin_kumar31 wrote:

just to clarify - i want to see my clock and the counter values in the waveforms. so that i can see the rising edge of the clock and the data values at that time and check for any race conditions? any way of doing that?


If you use the clock to sample data, then you can't also see the clock.  The data is sampled at the

rising edge of the clock, so any race conditions would show up as time jitter (+/- 1 cycle) on

the data samples.  If you really need to see higher frequency signals, you need to sample faster.

You could use a DCM or PLL to generate a faster sampling clock for ChipScope, but in the end

isn't seeing the data sampled on the original clock edge (just like it is your other logic) good enough?

 

-- Gabor

-- Gabor
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Explorer
Explorer
18,408 Views
Registered: ‎08-23-2011

Re: chipscope triggers and data collection setup ...

hi gabor .... 

 

i think i understand now - chipscope samples at a particular clk rate and the signals you can capture should be slower than the clock rate and to see setup/hold time violations, you can check the data from the rising edge of the clk shown by the nos. at the top. do let me know if my understanding is correct here?

 

i also want to know if its ok to map trigger/storage qualifiers to data ports? anything wrong with doing that so that i can see it with the waveforms itself for better verification?

 

lastly - suppose i give the give the fpga an input using a switch, whcih i press at random times , but i select that switch input as the clock in chipscope (sampled every rising edge), then will i be able to see data sampled at every rising edge of the input (i.e. when i press the switch). is there anything wrong with such a scheme? i am trying this now but its not working as expected, so is there anything conceptually wrong with what i am doing? 

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Professor
Professor
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Registered: ‎08-14-2007

Re: chipscope triggers and data collection setup ...

I think your understanding of the sampling is correct.

 

When I generate an ILA core I generally make the data and trigger connections the same.  Note

that the match units can generate functions based on multiple input bits so that you don't necessarily

see the trigger as a signal, but you can see all of the signals that caused the trigger to happen.

The waveform display also shows you the clock number where the trigger occured.  You won't

see the storage qualifier, just like you don't see the clock.  If the storage qualifier is false nothing

gets stored, so if you could look at it you'd see it always high.

 

Push-buttons are not appropriate as clock sources.  You would need to debounce the buttons

to get a single clean edge per press of the button.  So by the time you've done that it's just as

easy to use a free-running clock for everything in the design and just create a single clock-cycle

long pulse as the output of your button debouncer.  You could use that as the storage qualifier,

but remember that you'd need to press the button 1024 times to fill a 1024-deep buffer.  For

that reason you probably want to re-think your storage qualification.  Or you could set up the

button debouncer like a keyboard where holding the button pressed long enough causes

the debouncer to output a continuous string of pulses.

 

-- Gabor

-- Gabor
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Observer
Observer
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Registered: ‎06-23-2012

Re: chipscope triggers and data collection setup ...

Hi , I am also facing some trouble with chipscope .I am experimenting with a simple counter When I use chipscope inserter I am able to see my counter outputs in the chipscope pro analyzer but when I generate ILA and ICON using xilinx coregen and instantiate the same inside my design I am unable to trigger .Core is found in the analyzer but sample buffer never gets filled up when I trigger even the "immediate trigger " option didn't work.This must happen when clk is not flowing into the ILA instantiation but I am using the same clk every where , in fact the synthesis net-list also confirms that ILA and ICON are there. Can anybody tell me why this is happening
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