comparator in BlockDesign

[betontalpfa]

I want to compare (lessthan, greaterthen) two vector in BlockDesign.

Which is the simplest way to implement a compactor in BlockDesign?

[xilinxacct]

Is something like this what you are looking for?

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity VHDL_Binary_Comparator is
port (
inp-A,inp-B : in std_logic_vector(3 downto 0);
greater, equal, smaller : out std_logic
);
end VHDL_Binary_Comparator ;

architecture bhv of VHDL_Binary_Comparator is
begin
greater <= '1' when (inp-A > inp-B) else '0';
equal <= '1' when (inp-A = inp-B) else '0';
smaller <= '1' when (inp-A < inp-B) else '0';
end bhv;

P.S. If you find the help... please remember to give a Kudo and mark as solution accepted

[anunesgu · Accepted solution]

Hi @betontalpfa,

I understand you wanted to do this comparison in Block Design (IPI). Since there's no pre-created IP for that comparison, you can create a Verilog/VHDL file like the one @xilinxacct posted.

Then you add that file to your project sources, right-click on it and select "Add Module to Block Design".

Then that IP will be added to the Block Design canvas and you'll be able to connect your buses to it.

Please let us know if that helps you.

Thanks,