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hrmt
Explorer
Explorer
920 Views
Registered: ‎06-09-2018

debugging a statemachine in vivado ila

i wrote a state machine for detecting a string in input stream of my fpga (sequence detector).

i connected the falling edge of my i_clk to clock probe of ila (by connecting nclk <= not(i_clk) to clk probe of ila).

now when i see the input stream and state of state machine in ila , the state is two sample after correct position?

what is the problem?

my state machine is attached.

123.PNG
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anunesgu
Moderator
Moderator
878 Views
Registered: ‎02-09-2017

Hi @hrmt,

 

I'm not sure about this issue yet, but to start, why did you connect an inverted clock to the ILA, instead of the original clock for that net?

The ILA is supposed to be clock with the exactly the same clock and phase for the net being scoped.

Could you please try that and see if it changes anything?

 

Thanks,

Andre Guerrero

Product Applications Engineer

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hrmt
Explorer
Explorer
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Registered: ‎06-09-2018

Hi @anunesgu

 

why did you connect an inverted clock to the ILA, instead of the original clock for that net?

i captured data with falling edge of i_clk in my state machine, for this reason i connected not(i_clk) to ila clk probe.

 

The ILA is supposed to be clock with the exactly the same clock and phase for the net being scoped

how can i sample data on falling edge of clk in ila?

  

of course i connected my i_clk to ila probe clk but result is same as above.

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hrmt
Explorer
Explorer
841 Views
Registered: ‎06-09-2018

i understand my mistake, thanks @anunesgu

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