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Explorer
Explorer
11,909 Views
Registered: ‎03-13-2012

error : input pad net 'clk' is driving non-buffer primitives:

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hi

 

when I connect my clock signal to the chipscope for seeing the clock itself,, the following message appears.

 

ERROR:NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives:

 

how can I view clock signal on chipscope, since when I connect it to trigger, it is not a buffer element

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Instructor
Instructor
19,679 Views
Registered: ‎08-14-2007

Re: error : input pad net 'clk' is driving non-buffer primitives:

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ChipScope is a logic analyzer, not an oscilloscope.  Usually you don't view clocks, and you certainly don't view the same clock that is clocking the other signals you have captured.  Scoping the same clock you're using as the ChipScope clock will not show you a waveform, only a solid high or low depending the the routing delays to the analyzer inputs.  If you're scoping some other clock, make sure you're sampling it at least twice per (that clock's) period, preferably more if you want to see a reasonable representation of its waveform.

-- Gabor

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Moderator
Moderator
11,907 Views
Registered: ‎06-05-2013

Re: error : input pad net 'clk' is driving non-buffer primitives:

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Hi,

Please check the following link:-

 

http://forums.xilinx.com/t5/Implementation/Clock-pad-driving-non-buffer-primitives-even-though-I-have-a/td-p/94540

 

Thanks

 

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Instructor
Instructor
19,680 Views
Registered: ‎08-14-2007

Re: error : input pad net 'clk' is driving non-buffer primitives:

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ChipScope is a logic analyzer, not an oscilloscope.  Usually you don't view clocks, and you certainly don't view the same clock that is clocking the other signals you have captured.  Scoping the same clock you're using as the ChipScope clock will not show you a waveform, only a solid high or low depending the the routing delays to the analyzer inputs.  If you're scoping some other clock, make sure you're sampling it at least twice per (that clock's) period, preferably more if you want to see a reasonable representation of its waveform.

-- Gabor

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Explorer
Explorer
11,890 Views
Registered: ‎03-13-2012

Re: error : input pad net 'clk' is driving non-buffer primitives:

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ok I understand this thing. 

but then I have one more question...

 

the logic analyzer (in my case chipscope) has its own clock, right? hence it should have the capability to take (as a form of data signal) the clock signal for design. Since that clock for Design Under Test (DUT) is not at all acting as a clock for chipscope pro analyzer...right?

 

one more thing that the clock shown in the figure below is the sampling clock? right?

 

pro_clock.JPG

 

bests,

Jaffry

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Instructor
Instructor
11,867 Views
Registered: ‎08-14-2007

Re: error : input pad net 'clk' is driving non-buffer primitives:

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When you generated the ILA core, either with Core Generator or using the ChipScope Core Inserter, you connected a clock from your DUT to the ChipScope ILA clock input.  That is the sampling clock.  The clock you show in your screen shot is just for communication with the host PC, and usually runs much slower.

 

Typically in a synchronous design, you clock the ILA core with the same clock as the signals you want to sample.  Then you don't need to see the clock in the waveform display, as each sample will come one clock after the previous one, and the samples are numbered.

-- Gabor
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