cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
MGaber123
Visitor
Visitor
500 Views
Registered: ‎11-17-2020

hold time violation

Jump to solution

I have hold time in my code 

MGaber123_0-1625783221479.png

this is my code 

module FIFO_4outputs #(parameter DATA_WIDTH = 32,
/////////////////////////////////////
IFM_SIZE = 14,
IFM_DEPTH = 3,
KERNAL_SIZE = 2,
//////////////////////////////////////
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE)/2 + 1,
ADDRESS_SIZE_IFM = $clog2(IFM_SIZE*IFM_SIZE),
ADDRESS_SIZE_NEXT_IFM = $clog2(IFM_SIZE_NEXT*IFM_SIZE_NEXT),
FIFO_SIZE = (KERNAL_SIZE-1)*IFM_SIZE + KERNAL_SIZE)
(
input wire clk,
input wire reset,
input wire [DATA_WIDTH-1:0] fifo_data_in_A,
input wire [DATA_WIDTH-1:0] fifo_data_in_B,
input wire fifo_enable,
output [DATA_WIDTH-1:0] fifo_data_out_1,
output [DATA_WIDTH-1:0] fifo_data_out_2,
output [DATA_WIDTH-1:0] fifo_data_out_3,
output [DATA_WIDTH-1:0] fifo_data_out_4
);

reg [DATA_WIDTH-1:0] FIFO [ FIFO_SIZE-1 : 0] ;

integer i;
always @ (posedge clk,posedge reset)
begin
if(reset)
begin
for( i=0; i<FIFO_SIZE; i=i+1)
begin
FIFO[i] <= 0;
end
end

else if(fifo_enable)
begin
FIFO[1] <= fifo_data_in_A;
FIFO[0] <= fifo_data_in_B;
for( i=0; i<(FIFO_SIZE/2-1); i=i+1)
begin
FIFO[2*i+3] <= FIFO[2*i+1];
FIFO[2*i+2] <= FIFO[2*i];
end
end
end

assign fifo_data_out_1=FIFO[(KERNAL_SIZE-1)*IFM_SIZE+(KERNAL_SIZE-1)];
assign fifo_data_out_2=FIFO[(KERNAL_SIZE-1)*IFM_SIZE+(KERNAL_SIZE-2)];
assign fifo_data_out_3=FIFO[(KERNAL_SIZE-2)*IFM_SIZE+(KERNAL_SIZE-1)];
assign fifo_data_out_4=FIFO[(KERNAL_SIZE-2)*IFM_SIZE+(KERNAL_SIZE-2)];

endmodule

0 Kudos
1 Solution

Accepted Solutions
bruce_karaffa
Scholar
Scholar
449 Views
Registered: ‎06-21-2017

Hold time violations are fixed in Place & Route.  Run the complete implementation and see if you still have hold time violations.

View solution in original post

6 Replies
bruce_karaffa
Scholar
Scholar
474 Views
Registered: ‎06-21-2017

Please post the the whole timing report, not just a screenshot.  Some questions:  Is this post synthesis or post implementation?  Are you using a clock wizard to set up your clocking components?

0 Kudos
MGaber123
Visitor
Visitor
459 Views
Registered: ‎11-17-2020

I do synthesis and add constraint on clock only and don't use a clock wizard.

 

0 Kudos
bruce_karaffa
Scholar
Scholar
450 Views
Registered: ‎06-21-2017

Hold time violations are fixed in Place & Route.  Run the complete implementation and see if you still have hold time violations.

View solution in original post

MGaber123
Visitor
Visitor
385 Views
Registered: ‎11-17-2020

 yes, hold time violations are fixed in implementation, but I want to know why there are hold time violations in synthesis?

0 Kudos
joancab
Teacher
Teacher
381 Views
Registered: ‎05-11-2015

Sometimes it happens that timing "fails" at synthesis and "gets fixed" at implementation. That's perfectly fine, nothing wrong.

I think synthesis uses estimated timings because place and routing hasn't been done so any "failure" is not based on actual delays.

What a timing failure at synthesis means, to me, is that the design is near the edge ("near" meaning not as close as in "close to the edge"). Take it as a harmless warning.

0 Kudos
MGaber123
Visitor
Visitor
376 Views
Registered: ‎11-17-2020

OK thanks, @joancab

0 Kudos