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12,539 Views
Registered: ‎10-25-2009

how to preserve signal name for ila core

vivado version: 2013.4

FPGA version: v7

 

I found sometimes the signal name will be changed from HardWare Maneger Navigator.

 

It will be inconvenient in debugging process.

 

So how can I preserve the natual signal name (BTW, I insert ila core at design code--by instance it in code)?

 

Thanks

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8 Replies
Scholar dwisehart
Scholar
12,534 Views
Registered: ‎06-23-2013

Re: how to preserve signal name for ila core

I found that (* KEEP = "TRUE" *) in the source has some nasty side-effects in Vivado, so I removed them all.  Now I open the synthesized design and use the TCL Console to find the nets with get_nets or I track down renamed nets with the synthesized schematic.

 

If there is a better way, I am interested in hearing it.

 

Regards,

Daniel

 

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Xilinx Employee
Xilinx Employee
12,526 Views
Registered: ‎02-14-2014

Re: how to preserve signal name for ila core

Hello,

I think MARK_DEBUG attribute can be helpful in this case to preserve the signal. Setting MARK_DEBUG on a net in the RTL preserves it and make it visible in the netlist. This
allows it to be connected to the logic debug tools at any point in the compilation flow.
Regards,
Ashish
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Scholar dwisehart
Scholar
12,523 Views
Registered: ‎06-23-2013

Re: how to preserve signal name for ila core

Hello Ashish,

 

That is what I try to do in the XDC file, but get_nets will not find it if the synthesizer has already renamed it.

 

Are you suggesting put something like (* MARK_DEBUG = "TRUE" *) in the source?  I haven't tried that yet.

 

Thanks,

Daniel

 

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Scholar dwisehart
Scholar
12,520 Views
Registered: ‎06-23-2013

Re: how to preserve signal name for ila core

It looks like this has been fixed in 2014.2 with options for 2014.1 and earlier:

 

http://www.xilinx.com/support/answers/57727.html

 

Option 1 is what I am using.

 

Not sure Option 2 will give a usable design, but worth a try: it is easy to do and undo.

 

Not sure of the side effects of Option 3, but like Option 2 it might leave to an unusable design, though on a more limited scale, depending on what cells you mark.

 

Thanks,

Daniel

 

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Xilinx Employee
Xilinx Employee
12,518 Views
Registered: ‎02-14-2014

Re: how to preserve signal name for ila core

Hello,

 

According to the AR, it is recommended that you migrate to Vivado 2014.2 and then move forward with your design.

 

To give a try, put MARK_DEBUG on signals in your RTL which you want to debug so that synthesizer tool can preserve the corresponding signal in the netlist. In case tool still renames and unable to find the signal, you are having 3 Options in AR as a workaround.

Regards,
Ashish
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12,512 Views
Registered: ‎10-25-2009

Re: how to preserve signal name for ila core

Hi ashishd,

I insert ila core in my code.

 

If add the attribute before singal specification, then the ila core if need to be add into code too?

 

Thanks

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Xilinx Employee
Xilinx Employee
12,503 Views
Registered: ‎02-14-2014

Re: how to preserve signal name for ila core

Hello,

After you add attribute in your RTL, you can use core generator flow in which you can generate and customize ILA core and include .xci file in your design.
Is it the same thing you need to inquire about? If not please elaborate the issue.
Regards,
Ashish
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Scholar dwisehart
Scholar
12,495 Views
Registered: ‎06-23-2013

Re: how to preserve signal name for ila core

Has anyone tried option 2: set -flatten_hierarchy to "none".  When I just did it with Vivado 2014.1 I got 1500 warnings about undriven pins--but they are not undriven: the design would not work at all if they were undriven, in simulation or silicon.  Setting -flatten_hierachy back to "rebuilt" and all those warnings go away.

 

Very strange,

Daniel

 

 

2014-06-19_11-06-28.png

 

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