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Adventurer
Adventurer
2,526 Views
Registered: ‎01-10-2011

how to prevent Vivado debug from splitting buses into several ports

In Vivado 2017.4 I created a debug core using the "set up debug" wizard containing a port with a vector of signals. The "connect_debug_port" seems to be created correctly inn the resulting xdc file, but when I open the ILA in vivado, the vector is split into several probes. How can I prevent Vivado from doing this?

I saw a post in the forum that suggested the syntax "lsort -dictionary", but when I tried to modify the xdc file accordingly, Vivado gives a critical warning about lsort not being supported in xdc files.

The command in the xdc file looks something like this:

 

connect_debug_port u_ila_0/probe0 [get_nets [list {signal[0]} {signal[1]} ..... {signal[80]}]]

 

and the probes in  the resulting ILA seem to split something like this:

probe_0[11:0]

probe_1[60:12]

probe_2[80:61]

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Moderator
Moderator
2,490 Views
Registered: ‎10-19-2011

You might try using the mark_debug property on the nets you want preserved. Are you using Synplify/3rd party synth tool, or Vivado's?

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Adventurer
Adventurer
2,431 Views
Registered: ‎01-10-2011

Maybe I didn't describe the problem correctly. Of course, the signals are already marked as debug in the design. This is happening when I set up the debug cores after the synthesis, where I assign the (marked debug) signals to ports on an ILA debug core. Even though I connect them to an appropriately sized port (meaning the same width of the port as the size of the vector), the implemented debug core seems to want to split some of the vectors into different ports with slices of the vector.

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Moderator
Moderator
2,420 Views
Registered: ‎10-19-2011

Do all the signals make it to the debug core, or are you seeing some signals missing? Are you able to reconstruct the bus in HW manager, you could use that as a possible work around?
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Moderator
Moderator
2,407 Views
Registered: ‎10-19-2011

One of my colleagues ran into a similar issue, re-generating the ltx from the implemented design fixed their problem. In the auto generated LTX, are the buses split already/missing?
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Observer
Observer
1,806 Views
Registered: ‎07-11-2018

I have this problem now with latest Vivado 2018.2. Is there a solution? How do you re-generating the ltx from the implemented design?

Timely responses appreciated. Thanks!
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Moderator
Moderator
1,798 Views
Registered: ‎02-09-2017

You can regenerate the LTX fie using the TCL command write_debug_probes <your_location>/debug_probes.ltx

 

If just that doesn't work, another workaround would be to  apply a DONT_TOUCH to the parent nets of the net segments marked for debug:

set_property DONT_TOUCH 1 [get_nets [get_property PARENT <net marked for debug> ] ]

 

This should prevent the nets from getting split or optimized. After that, you would need to run opt_design again, followed by the write_debug_probes command to generate the new LTX

 

Thanks.

Andre Guerrero

Product Applications Engineer

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Participant
Participant
788 Views
Registered: ‎05-16-2018

Another way to solve this is to open the final design checkpoint. 

  • Change the window layout to ECO
  • Click "Write Debug Probes" listed in the ECO Navigator pane on the left side of the screen. (this calls write_debug_probes)

On a side note for anyone who hasn't tried the ECO related functions, I have found them very useful for debug. 

If you haven't tried the "Replace Debug Probes" feature you are missing out.