opt_design fails after inserting ila cores

[thommythomaso]

Hello,

I tried to instanciate an ILA core in my design to opserve signals on the FPGA. With the ILA core in the design, opt_design fails with the following error:

Starting Logic Optimization Task
INFO: [Mig 66-82] Memory netlist is in sync with memory I/O ports assignments.

Phase 1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : WRAPPER_INST/CL/CL_DEBUG_BRIDGE/inst/xsdbm 
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell xsdbm_CV.
ERROR: [Chipscope 16-331] dcp file did not get generated for instname : xsdbm 
ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed 
Phase 1 Generate And Synthesize Debug Cores | Checksum: 1ce97c06d

Do I miss an important step while including the ILA?

Thanks!

[baltintop]

Hi @thommythomaso 

How did you insert the ILA cores? I suggest using Set Up Debug tool to avoid any mistakes.

[thommythomaso]

I created both the debug_bridge and the ila core with the ip creator. I instanciated them in the top level of my fpga design, connected the ila to the axi bus of interest and the debug_bridge to the jtag port.

I manually conected the ILA to the core with the connect_debug_cores tcl command.

At which stage of the flow do I have to use the Set Up Debug tool?

[baltintop]

Hi @thommythomaso 

• Synthesize the design
• Open the synthesized design and select the wires you want to debug on the schematic
• Click on Set Up Debug, configure it, save the changes and it will insert the debug cores for you
• Implement the design

[dpaul24]

@thommythomaso,

try once again after re-generating the ILA core, i.e. make sure the ILA core is generated (and not just instiantiated) before synthesis begins.

[thommythomaso]

I already have regenerated the ILA and the debuge bridge twice. The ip is up to date and the initial synthesis finishes without any issues. Implementation just fails.

[anunesgu]

Hi @thommythomaso,

Is there any special reason you are including the Debug Bridge? the ILA does not need one to work, except in very specific cases such as designs with Partial Reconfiguration (PR) or Xilinx Virtual Cable (XVC) projects.

It's probably the reason why your design is failing Implementation. Vivado might probably be failing to figure out how to connect and physically place the ILA and Debug Bridge together.

I suggest you follow the previous suggestion and remove the ILA and Debug Bridge from your HDL code and use the Setup Debug feature instead, after you've ran the synthesis.

The document Vivado Design Suite Tutorial Programming and Debugging - UG936, Lab 1, pg.13 has a tutorial that explain the process to insert the ILA.

Thanks,