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Participant
Participant
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Registered: ‎01-26-2020

problem impleminting system ILA

Hello

 

I am trying to use system ILA to debug one of my designs and it refuses to work no matter what I do and always give me the error message bellow. It works fine with other designs but not this one. I even re do the design from scratch and it still not working.

 

WARNING: [Labtools 27-3413] Dropping logic core with cellname:'CL_Zcode_Design_i/system_ila_0/U0/ila_lib' at location 'uuid_F6565DAB05BA549A91A4855DC8FD4DF8' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file(s) C:/FPGA_Projects/My_Designs/CL_Test3_Zcode_FromZero/CL_Test3_Zcode_FromZero.runs/impl_1/CL_Zcode_Design_wrapper.ltx.
The device design has 1 ILA core(s) and 0 VIO core(s). 0 ILA core(s) and 0 VIO core(s) are matched in the probes file(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

 

Do you have any idea what is the problem and how to solve it.

 

Thank you

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2 Replies
Moderator
Moderator
247 Views
Registered: ‎02-09-2017

Hi @ashura12,

Thank you for contacting us about this issue.

I noticed you are using a Zynq device. Could you please inform where the clock for the System ILA (and for the rest of the logic) is coming from? Is it a clock coming from the PS? If you are able, could you please post a picture of the Block Diagram?

We normally see this issue when the clock that is being fed to the ILA is not a free-running clock. 

Specially for user of Zynq devices, the resources in the PS side are not enabled automatically.

You need to first export your project to SDK and run a basic "Hello World" project. Within that project there will be a script called init_ps7.tcl, which will initialize all the PS resources such as memories, GPIOs, Clocks, etc.

Then, you can go back to Vivado, reprogram the bitstream into the FPGA (or you can also have SDK do it for you) and you'll be able to see the debug cores.

The document Vivado Design Suite Tutorial Embedded Processor Hardware Design - UG940, Lab 1, starting on Step 6, has a good example of the process above described.

Could you please try the above process and let us know if it works?

Please let us know if you have any questions.

Thank you,

Andre Guerrero

Product Applications Engineer

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Participant
Participant
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Registered: ‎01-26-2020

Hi @anunesgu 

Thank you for your response

I am designing a signal receiver from an external device and I am doing some signal processing things for experiment. The device has 4 data channels and clock signal. I build a simple design to read the signal as is and PLL to have two clocks one is the same as the original and the other multiply by 4. I used ILA to display the signals using the faster clock and it works fine. When I complete my design and added the signal processing blocks, I used ILA with the same fast clock to display the output but I get the above error.

I tried using the slower clock and it works fine with the complete design but the fast clock always giving me the same error.

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