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santukms
Adventurer
Adventurer
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Registered: ‎09-15-2010

problem with the secureip in the ise12.2

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hi all....

 

i am using the coregen ip endpoint block plus v1.14 for the pcie on the board ml555 xc5lx50t.

 

now in the simuation of the example design i got the following error...

 

vsim work.board glbl
# vsim work.board glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/EDA/QuestaSim/v6_6/examples/work/GTP_DUAL.v(3490): Module 'GTP_DUAL_FAST' is not defined.
# ** Error: C:/EDA/QuestaSim/v6_6/examples/work/GTP_DUAL.v(3490): Module 'GTP_DUAL_FAST' is not defined.
# Optimization failed
# Error loading design

 

here before doing this i compiled the precompiled libraries using the compxlib of xilinx ,

it generated the following libraries

secureip

simprim

simprims_ver

edk

unimacro

unimacro_ver

unisim

unisim_ver

xilinxcorelib

xilinxcorelib_ver

 

 

here the secureip generated is in the encryted form.....

 

 

now i am using the secureip library in questasim....and got the above error

 

 

is the things what i have done is correct ,,,,,

can any one tell me how to handle the secreip in the questasim.......

 

 

Thanks in advance.....

 

 

 

 

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santukms
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Registered: ‎09-15-2010
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duthv
Xilinx Employee
Xilinx Employee
4,533 Views
Registered: ‎09-14-2007

Hi,

 

Since SecureIP is a library and you are running Verilog simulation you need to have the -L secureip switch as part of your simulation. Actually you will need -L secureIp, -L unisims_ver and possibly xilinxcorelib too depending on what you have in your design.

 

More information in the Synthesis and Simulation Design Guide and:

 

http://www.xilinx.com/support/answers/32936.htm

 

Thanks

Duth

 

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santukms
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Registered: ‎09-15-2010
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