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Visitor
Visitor
2,774 Views
Registered: ‎02-13-2017

problems with VIO

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hello

I am studying the use of VIO in a simple program. Enter a binary number by VIO and turn on that number in the leds of the fpga. But i get this error

 

[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net PROBE_IN0[0] has multiple drivers: i_7/O, U_VIO/inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/Probe_out_reg[0]/Q.

 

program top

 

entity LEDS_VIO is

end entity;

architecture Behavioral of LEDS_VIO is

signal Entrada : std_logic_vector(7 downto 0);
signal Salida : std_logic_vector(7 downto 0);
signal clk : std_logic;

component LEDS is
port
(
clk : std_logic;
Entrada : in std_logic_vector(7 downto 0);
Salida : out std_logic_vector(7 downto 0)
);
end component;

component vio_0 is
port
(
CLK : IN STD_LOGIC;
PROBE_IN0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PROBE_OUT0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;

begin

U_VIO : vio_0
port map
(
CLK => clk,
PROBE_IN0(7 downto 0) => Entrada,
PROBE_OUT0(7 downto 0) => Salida
);

u_LEDS: LEDS port map
(Entrada => Entrada,
 Salida => Salida,
 clk => clk
 );

end Behavioral;

 

other part of the program

 

entity LEDS is
Port ( clk : in std_logic;
Entrada : in STD_LOGIC_VECTOR (7 downto 0);
Salida : out STD_LOGIC_VECTOR (7 downto 0));
end LEDS;

architecture Behavioral of LEDS is

begin

Salida <= Entrada;

end Behavioral;

 

thanks for the help

 

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1 Solution

Accepted Solutions
Voyager
Voyager
4,632 Views
Registered: ‎04-21-2014

You have connected the "Salida" output port of vio_0 with the output port "PROBE_OUT0" of  vio_0. Hence, the two drivers message.  It's a good thing that Vivado issued a DRC violation, because bad things would ensue if it did not.

 

In any event, a VHDL course might help here...worth considering.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

View solution in original post

1 Reply
Voyager
Voyager
4,633 Views
Registered: ‎04-21-2014

You have connected the "Salida" output port of vio_0 with the output port "PROBE_OUT0" of  vio_0. Hence, the two drivers message.  It's a good thing that Vivado issued a DRC violation, because bad things would ensue if it did not.

 

In any event, a VHDL course might help here...worth considering.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

View solution in original post