UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
766 Views
Registered: ‎05-14-2015

"greater than" trigger of ILA

Hello, I used ILA to capture some data. 

I'm trying to use "probe29[31:0]" as a trigger with "greater than" condition. But, when I run this trigger, Vivado reports the error like below. Do you know why?

 

 

"[Labtools 27-3258] Due to ILA core feature implementation, probes which do not match the complete ILA core probe port from MSB to LSB may only use operator 'eq' or 'neq'. 
hw_ila 'hw_ila_1' hw_probe 'i_cputop/g_CPUbridge_VirtualJTAG.i_IPG1_VirtualJtag/delay_cnt[31:0]' with MAP property 'probe29[31:0]' uses operator 'gt' in compare value 'gt32'h0000_0010'."
0 Kudos
3 Replies
Scholar dpaul24
Scholar
747 Views
Registered: ‎08-07-2014

Re: "greater than" trigger of ILA

@softwind555,

 

Are you setting the complete 32 bit value for probe29[31:0]?

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
718 Views
Registered: ‎05-14-2015

Re: "greater than" trigger of ILA

Hello, @dpaul24

Yes. Please find the code slice below: 

	COMPONENT ila_virtual_jtag

PORT (
	clk : IN STD_LOGIC;
	probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
	probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe10 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 
	probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe13 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe14 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
	probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 
	probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe21 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); 
	probe22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe24 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
	probe25 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 
	probe26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
	probe27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
	probe28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
	probe29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	probe30 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT  ;
signal delay_cnt :			unsigned(31 downto 0) := (others=>'0');

i1_ila_virtual_jtag : ila_virtual_jtag
	PORT MAP (
		clk => CPU_Clk,

		probe0(0) => Reset, 
		probe1 => iCPU_Address, 
		probe2 => iCPU_WData, 
		probe3(0) => iCPU_Write, 
		probe4 => (others => '1'), 
		probe5(0) => iCPU_RRequest, 
		probe6 => CPU_RData, 
		probe7(0) => CPU_RAck, 
		probe8(0) => CPU_Int, 
		

		probe9 => AWADDR, 
		probe10 => AWPROT, 
		probe11 => AWVALID, 
		probe12 => AWREADY, 
		probe13 => WDATA, 
		probe14 => WSTRB, 
		probe15 => WVALID, 
		probe16 => WREADY, 
		probe17 => BRESP, 
		probe18 => BVALID, 
		probe19 => BREADY, 
		probe20 => ARADDR, 
		probe21 => ARPROT, 
		probe22 => ARVALID, 
		probe23 => ARREADY, 
		probe24 => RDATA, 
		probe25 => RRESP, 
		probe26 => RVALID, 
		probe27 => RREADY,
		probe28 => (others => '1'),
		probe29 => std_logic_vector(delay_cnt),
		probe30 => std_logic_vector(delay_cnt_max)
0 Kudos
Visitor iprop1
Visitor
343 Views
Registered: ‎11-02-2018

Re: "greater than" trigger of ILA

I found a potential solution - don't know if it will help you or not.   

Here is the message I was getting:
[Labtools 27-3258] Due to ILA core feature implementation, probes which do not match the complete ILA core probe port from MSB to LSB may only use operator 'eq' or 'neq'.
hw_ila 'hw_ila_1' hw_probe 'XXXXXX[63:0]' with MAP property 'probe13[63:0]' uses operator 'gt' in compare value 'gt64'h0000_0000_0000_0004'.

What I found out was that my xdc file had the bus as {XXXXXX[0],XXXXXX[1],......,XXXXXX[63]}

I opened my LTX file and noticed that my bus was ordered as XXXXXX[63],XXXXXXX[62], .... XXXXXX[0].

Now, both of these files were never modified by me; both are autogenerated by Vivado.  One during the setup debug step (as a save to the constraints file) and the other when the bitstream is created.

I hand edited the LTX to reverse the bits so that it now was XXXXXX[0],XXXXXX[1]....XXXXXX[63] to match how my xdc was, and now, I can now do > and < operations!

I'm using 2018.2 and the my chipscope worked for several weeks with no issues, and then all of a sudden, I started getting the error I posted.  I tried closing Vivado and reopening as another post suggested, but that did not help.  I tried many things until I did the above file edit.

Good luck - and I hope this helps

Hiren

 

0 Kudos