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Observer creedxilinx
Observer
10,659 Views
Registered: ‎01-26-2012

rebuilding an reference design to add chipscope

I am running the PCIE reference design on an ML605 board.  I would like to look at differnt points in the design using chipscope, but I'm not sure how to rebuild the design.  The design that is generated by IP core is implemented using

a script to generate the bitfile.  I'm trying to find the IPCore generated project or verilog source that instantiates the PCIE core that was generated so that I can build a project in ISE to add chipscope in to look at the data as it moves through the

design.

 

The implementation script and the windows command file it uses are attached in case it helps to identify a file that could be pulled into an ISE project to add chipscope.

 

Thanks,

 

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2 Replies
Xilinx Employee
Xilinx Employee
10,636 Views
Registered: ‎07-01-2008

Re: rebuilding an reference design to add chipscope

Chipscope issues are covered at the Design Tools - Others forum:

http://forums.xilinx.com/t5/Design-Tools-Others/bd-p/OTHER

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Moderator
Moderator
10,625 Views
Registered: ‎04-17-2011

Re: rebuilding an reference design to add chipscope

If you want to do the project from RTL level, look for a file named: xilinx_pcie_2_0_ep_v6.prj in your project directory. Open that. You would see a list of files. Go ahead and create a new project in ISE and add those files. Top module should be xilinx_pcie_2_0_ep_v6. Additional Synthesis settings:
-ifmt VERILOG
-use_dsp48 no
-bufg 0
-opt_mode SPEED
-opt_level 2
-max_fanout 100
-use_sync_reset yes
-uc xilinx_pcie_2_0_ep_v6.xcf

For the switch details refer to XST User Guide online.
You can then use the CDC flow to add chipscope and debug.

Alternately, you can also just add the synthesized xilinx_pcie_2_0_ep_v6.ngc file and then add CDC file to set-up chipscope (but it wont be a RTL project). Ensure you select EDIF/NGC when creating the project.

Hope this helps.
Regards,
Debraj
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