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ronnywebers
Advisor
Advisor
6,410 Views
Registered: ‎10-10-2014

remove all mark debug from (hierarchical) block design all at once

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I have a large block design consisting of some sub-designs. On many signals in the block design I've put 'mark debug' symbols, like this :

 

mark debug.jpg

now, as I have many of them, all spread around the design (not this one, this is just a simple example), is there a way to remove all the debug marks at once?

 

I've tried a tcl command like this :

 

set_property mark_debug false [get_nets –hier [list {*}]]

but then Vivado says I have no (elaborated, synthesized or implemented design) open, which is indeed the case. So is there another way to remove the marks (without missing one) from the block design?

 

Or is there no need to do this, and can I just stop after synthesis, make sure they are not setup as debug signals, and generate a bitstream without an ILA in it?

 

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arpansur
Moderator
Moderator
10,360 Views
Registered: ‎07-01-2015

Hi @ronnywebers,

 

You can make use of below commands for BD. If nothing is true you are good to go:

get_property HDL_ATTRIBUTE.MARK_DEBUG [get_bd_intf_nets *]

get_property HDL_ATTRIBUTE.MARK_DEBUG [get_bd_nets *]

 

After opening synthesized design you can use below command:

get_property mark_debug [get_nets -hierarchical -regexp -nocase -top_net_of_hierarchical_group ".*" ]

Thanks,
Arpan
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3 Replies
arpansur
Moderator
Moderator
6,405 Views
Registered: ‎07-01-2015

Hi @ronnywebers,

 

Can you please try

set_property HDL_ATTRIBUTE.MARK_DEBUG false [get_bd_nets *]

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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ronnywebers
Advisor
Advisor
6,032 Views
Registered: ‎10-10-2014

yes I tested this on a design, that works for me!

 

I also needed to use :

 

set_property HDL_ATTRIBUTE.MARK_DEBUG false [get_bd_intf_nets *]

to get rid of some debug marks on intf_nets

 

same is probably true for external interfaces?

 

guess there's no command to do this all at once?

 

Is there also a command to list all mark debugs? So I can verify wether they were really removed, instead of browsing the whole design tree?

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
arpansur
Moderator
Moderator
10,361 Views
Registered: ‎07-01-2015

Hi @ronnywebers,

 

You can make use of below commands for BD. If nothing is true you are good to go:

get_property HDL_ATTRIBUTE.MARK_DEBUG [get_bd_intf_nets *]

get_property HDL_ATTRIBUTE.MARK_DEBUG [get_bd_nets *]

 

After opening synthesized design you can use below command:

get_property mark_debug [get_nets -hierarchical -regexp -nocase -top_net_of_hierarchical_group ".*" ]

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post