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Registered: ‎12-26-2013

report_power incorrect clock estimation, maybe incorrect power when not starting SAIF from 0 time

My aim is to accurately measure power during a window of intense switching activity that does not include the start-up and reset sequence in Vivado with Xpower on a design implemented in Virtex 7 980T.


To do this, I am simulating the design in ncsim (backannotated with sdf) and capturing the simulation activity into a SAIF format binary dump file. I them read the dump file into Vivado with the implemented (placed and routed) design open using read_saif. After reading the saif file in I run report_power to obtain the power from the design annotated with actual switching activity. The saif read appears successful (see below)



read_saif -no_strip {/work/justin/ldpc/proton_ldpc_fpga/ldpc/vivado/proton_ldpc_xfpga/dec_sp_top_wrapper.saif}
INFO: [Power 33-167] Parsing SAIF file /work/justin/ldpc/proton_ldpc_fpga/ldpc/vivado/proton_ldpc_xfpga/dec_sp_top_wrapper.saif
INFO: [Power 33-26] Design nets matched = 32301 of 32301
INFO: [Power 33-177] SAIF annotation done from file /work/justin/ldpc/proton_ldpc_fpga/ldpc/vivado/proton_ldpc_xfpga/dec_sp_top_wrapper.saif
read_saif: Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 7334.922 ; gain = 0.000
report_power -file dec_sp_top_saif_high_confidence_5_vectors_pwr.txt
report_power: Time (s): cpu = 00:00:21 ; elapsed = 00:00:11 . Memory (MB): peak = 7334.922 ; gain = 0.000


I have verified the saif file by inspection of an equivalent vcd dump, and that it only captures the switching period of interest. My expectation of the outcome of this procedure is that report_power will annotate node switching activity based on the number of switching events that occur between the start of the event capture period and the end of the event capture period in the SAIF fie.


There appear to be two problems:

1. The clock estimation appears to determine the clock based (my guess) on the ENTIRE period of the simulation from time zero, even though I do not begin to capture data until well into the simulation. This results in the power report providing a wildly incorrect estimation of clock activity. My clock is constrained to 12ns and is reported as such in implementation. The clock in the waveform captured is 12ns period.


2.2 Clock Constraints

| Clock   | Domain  | Constraint (ns) |
| clk_dec | clk_dec |          3471.8 |


2. Inferring from the above, the power report is likely to be also incorrect as it seems to average switching activity over the entire simulation period from time zero, not just during the time of interest.


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2 Replies
Registered: ‎12-26-2013


This is the author of the original posting with an addendum.


I was hoping that someone at Xilinx might be able to offer a solution to the problem identified in this posting, that is, how to obtain an accurate power report and a correct clock constraint analysis from a SAIF-based activity factor for a window of interest in a simulation.


I have attached an abbreviated version of the power report to assist with the analysis.





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Xilinx Employee
Xilinx Employee
Registered: ‎10-28-2013



This is strange. You could validate the correctness as:


    Check the following things in your SAIF:

         - Check the total duration



        - Check the activity rate on the clock:

               TC  - Toggle count

               and also  T1  & T0 - to make sure there is enough and equal time period the clock in both '0'and '1


Now you can calculate the frequency as:

       Toggle rate: TC/DURATION

           Frequency = TC/2  , then you can convert it into time period (ns).


Since you are using Vivado, you must be having .dcp files.


Please share the .dcp (post route)  and saif (post rout netlist simulation), we could look at it and get back to you.



Power Analysis & Optimization
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