running set up debug for a 2nd time (to add extra signals) causes errors

[ronnywebers]

Using Vivado 2015.4

phase 1 :

-----------

1. I synthesise a design, then open it, and run 'set up debug'
2. Then I add some signals I want to see on my ILA
3. Then hit 'generate bitstream'
4. Vivado asks me if I want to save changes
5. I say 'yes'
6. -> ILA constraints are saved to the target xdc file
7. bitstream generation starts & completes
8. I debug with the ILA, and decide I need to see some extra signals.

phase 2:

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1. I open again the synthesised design
2. I click on set up debug
3. I select 'continue to debug xx nets'
4. I deselect 'debug xx new nets'
5. then in the dialog, I search for the extra signals I need, and add them
6. I complete the dialog and hit 'generate bitstream'
7. again Vivado asks me to save the changes
8. I confirm with yes, changes are saved to the target xdc file. I checked and the xdc contents seem to be replaced, or at least the extra debug probes are added. 
9. Bitstream generation starts.

Now : somewhere during bitstream generation (looks like implementation phase), I get a pop-up with a critical message : [Common 17-162] Invalid option specified for '-nets'. [/path_to_my_xdc:171]

In the log file I found this :

Parsing XDC File [/home/zynqdev/Zynq/2015_4/drfa/zynqsnap/Vivado/src/constraints/mark_debug.xdc]
WARNING: [Vivado 12-507] No nets matched 'u_ila_0_clk_out1'. [/home/zynqdev/Zynq/2015_4/drfa/zynqsnap/Vivado/src/constraints/mark_debug.xdc:171]
CRITICAL WARNING: [Common 17-162] Invalid option value specified for '-nets'. [/home/zynqdev/Zynq/2015_4/drfa/zynqsnap/Vivado/src/constraints/mark_debug.xdc:171]
Finished Parsing XDC File [/home/zynqdev/Zynq/2015_4/drfa/zynqsnap/Vivado/src/constraints/mark_debug.xdc]

line 171 of the mark_debug.xdc contains (complete file attached)

connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1]

However, bitstream generation completes ok, and the ILA has the signals added.

This issue seems to appear systematically, each time I 're-edit' the setup debug configuration ...should I worry about this? Or am I doing something wrong? Should I clear the contents of the .xdc file before I save the synthesised design?

Also, do I need to re-run synthesis after these debug probe changes, or can I force synthesis 'up-to-date'?

[arpansur]

Hi @ronnywebers,

As long as clock connectivity of debug hub is okay you should not worry.

[ronnywebers · Accepted solution]

@arpansur, after running into some more errors during 'incremental set up debug cycles', I found the cause. Here are the critical warnings I get at the moment :

1) the first 2 warnings refer to constraints in the very beginning of the xdc file, that try to connect u_ila_x_clk_out1 to the dbg_hub/clk. But they are put in the xdc file (by Vivado's setup debug wizard) before the actual 'create_debug_core' statement :

connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1]

connect_debug_port dbg_hub/clk [get_nets u_ila_0_0_clk_out1]

create_debug_core u_ila_0_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0_0]

also, the very first line tries to connects  u_ila_0_clk_out1, while the debug core is named u_ila_0_0. So this looks like a 'leftover' from some previous debug core. 

So I commented out the first 2 lines, this clears the first 2 critical warnings

2) the third warning points to the very last line in the xdc file :

...
connect_debug_port u_ila_0_0/probe50 [get_nets [list design_1_i/snap_SNAP_IO_27_io_wr_full]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1]

again here is a left-over constraint from a previous debug setup, as u_ila_0_clk_out1 does not exist, it should be u_ila_0_0_clk_out1

so this looks like some bugs in Vivado, having difficulties when you re-run the 'set up debug wizard' a few times.

so I modified the last line to u_ila_0_0_clk_out1, and this clears the third critical warning !

note that bitstream generation was always successful, and the ILA operated correctly too, despite the critical warnings - so Vivado did connect the clock anyway, even with the error in the very last line of the xdc file... kind a strange ...