03-20-2012 01:05 PM
im using chipscope pro with ISE 10.1 ... for some reason, one of the trigger nets that I have, it keeps getting optimized and so it does not show up in the modify net connections panel of chipscope. the other nets show up properly
i wanted to know if this is actually because the net is being optimized by chipscope or XST and so is being removed or for some other reason.
Also, is there any way around this?
please do let me know ...
03-20-2012 01:57 PM
I believe that only sythensis can optimize out a net (XST in this case). There are attributes that can be placed in the RTL (verilog or VHDL) like KEEP and SAVE (go read what these do, and how to use them) to prevent synthesis from optimizing signals away.
03-20-2012 03:31 PM
I read this on the xilinx website ...
Logic trimming is the removal of logic that is unused because it has no driver, no load, or no effect on any chip outputs. For example, a state machine whose outputs are used only as feedback to its inputs can be removed without affecting the operation of the design.
So for the signal that's being trimmed out, I connected it to an LED so that it drives a LOAD (as mentioned above). However, when I run XST again, I still don't see the signal. I guess XST has no direct link with the .UCF file so if I first implement my design, then include the chipscope analyser, resynth. the design and look at chipscope "modify net connections" tab, will that help in seeing the trimmed out pin?
03-20-2012 07:28 PM
I'm not sure what you added to your .ucf file, but that's not the place to add a KEEP attribute.
KEEP should be in the source code. As for adding a connection to an LED output, that
needs to happen in the source also. I don't think that there is any back-annotation to
the synthesis netlist after translation.
Another possibility if you don't see a net even though it drives an output load is that
the net has been re-named. Remember that the synthesis netlist will flatten nets
over the hierarchy. So if you have a net that starts at a lower level module, but connects
up to higher levels through the module ports, only the name of the net at the highest
level of instantiation will still exist in the netlist after synthesis.
03-21-2012 03:41 AM
03-23-2012 12:40 PM
yes ... thanks all for your inputs ...
the keep attribute helps. though i wanted to know if i can use this keep attribute for only the signals in top level vhd module or other signals buried in the sub modules as well?
and is it advisable to bring out the signals you want to see on chipscope to the top level or is it ok to use the keep attribute in a lower module and try and check those signals using chipscope? for me, it works better when i bring out those signals in the top level ... in the lower level, even if i use the keep attribute, i sometimes dont see the signals in the modify nets window of chipscope ... so any suggestions for this?
thanks in advance ...
03-26-2012 07:15 AM
04-12-2012 05:33 AM
Could someone tell me how do we write the keep attribute?
Do we need to write it only once or for all the signals. I would be thankful if someone could tell me an example of the same.
04-17-2012 08:45 AM