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zubin_kumar31
Explorer
Explorer
11,007 Views
Registered: ‎08-23-2011

some nets not showing up in chipscope "modify net connections" tab ...

im using chipscope pro with ISE 10.1 ... for some reason, one of the trigger nets that I have, it keeps getting optimized and so it does not show up in the modify net connections panel of chipscope. the other nets show up properly

 

i wanted to know if this is actually because the net is being optimized by chipscope or XST and so is being removed or for some other reason. 

 

Also, is there any way around this?

 

please do let me know ...

 

Thanks, 

Z.

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8 Replies
austin
Scholar
Scholar
11,005 Views
Registered: ‎02-27-2008

Z,


I believe that only sythensis can optimize out a net (XST in this case).  There are attributes that can be placed in the RTL (verilog or VHDL) like KEEP and SAVE (go read what these do, and how to use them) to prevent synthesis from optimizing signals away.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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zubin_kumar31
Explorer
Explorer
10,998 Views
Registered: ‎08-23-2011

Hi,

 

I read this on the xilinx website ...

 

Logic trimming is the removal of logic that is unused because it has no driver, no load, or no effect on any chip outputs. For example, a state machine whose outputs are used only as feedback to its inputs can be removed without affecting the operation of the design. 

 

So for the signal that's being trimmed out, I connected it to an LED so that it drives a LOAD (as mentioned above). However, when I run XST again, I still don't see the signal. I guess XST has no direct link with the .UCF file so if I first implement my design, then include the chipscope analyser, resynth. the design and look at chipscope "modify net connections" tab, will that help in seeing the trimmed out pin? 

 

Z.

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gszakacs
Instructor
Instructor
10,995 Views
Registered: ‎08-14-2007

I'm not sure what you added to your .ucf file, but that's not the place to add a KEEP attribute.

KEEP should be in the source code.  As for adding a connection to an LED output, that

needs to happen in the source also.  I don't think that there is any back-annotation to

the synthesis netlist after translation.

 

Another possibility if you don't see a net even though it drives an output load is that

the net has been re-named.  Remember that the synthesis netlist will flatten nets

over the hierarchy.  So if you have a net that starts at a lower level module, but connects

up to higher levels through the module ports, only the name of the net at the highest

level of instantiation will still exist in the netlist after synthesis.

 

-- Gabor

-- Gabor
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rcingham
Teacher
Teacher
10,989 Views
Registered: ‎09-09-2010

"I guess XST has no direct link with the .UCF file"

Correct. XST does not read the UCF. XST reads a XCF file if directed to. Open the Synthesis Properties window by right-clicking 'Synthesis - XST' in the Processes window, and the relevant features are 4th and 5th on the list.

I generally put KEEP attributes in the HDL, as Gabor suggests, however, and often so that they remain available for input to ChipScope.

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"If it don't work in simulation, it won't work on the board."
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zubin_kumar31
Explorer
Explorer
10,981 Views
Registered: ‎08-23-2011

yes ... thanks all for your inputs ...

 

the keep attribute helps. though i wanted to know if i can use this keep attribute for only the signals in top level vhd module or other signals buried in the sub modules as well?

 

and is it advisable to bring out the signals you want to see on chipscope to the top level or is it ok to use the keep attribute in a lower module and try and check those signals using chipscope? for me, it works better when i bring out those signals in the top level ... in the lower level, even if i use the keep attribute, i sometimes dont see the signals in the modify nets window of chipscope ... so any suggestions for this?

 

thanks in advance ...

Z.

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rcingham
Teacher
Teacher
10,972 Views
Registered: ‎09-09-2010

"i wanted to know if i can use this keep attribute for only the signals in top level vhd module or other signals buried in the sub modules as well?"

Anywhere you like.
However, if you don't set the XST '-keep_hierarchy' option, it may still be hard to find the signals in the ChipScope GUI.

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"If it don't work in simulation, it won't work on the board."
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akanksha112
Adventurer
Adventurer
10,954 Views
Registered: ‎04-07-2011

Hi All

 

Could someone tell me how do we write the keep attribute?

Do we need to write it only once or for all the signals. I would be thankful if someone could tell me an example of the same.

 

 

 

 

akanksha

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rcingham
Teacher
Teacher
10,948 Views
Registered: ‎09-09-2010

Read The Fine Constraints Guide.
It is probably 'cgd.pdf'. Search for 'KEEP'.

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"If it don't work in simulation, it won't work on the board."
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