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ggillett
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Registered: ‎08-14-2018

system ILA is a pain in the A

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Reconfiguring the IP often crashes Vivado. 

#  EXCEPTION_ACCESS_VIOLATION (0xc0000005) at pc=0x00007fffbe4aae7f, pid=520, tid=12380
#
# JRE version: Java(TM) SE Runtime Environment (9.0+11) (build 9.0.4+11)
# Java VM: Java HotSpot(TM) 64-Bit Server VM (9.0.4+11, mixed mode, tiered, compressed oops, g1 gc, windows-amd64)
# Problematic frame:
# C  [librdi_device.dll+0x64ae7f]
#
# No core dump will be written. Minidumps are not enabled by default on client versions of Windows
#
# An error report file with more information is saved as:
# c:\Users\ggillett\Documents\repos\pynqpitaya\hs_err_pid520.log
#
# If you would like to submit a bug report, please visit:
#   http://bugreport.java.com/bugreport/crash.jsp
# The crash happened outside the Java Virtual Machine in native code.
# See problematic frame for where to report the bug.
#

Removing it and re-instantiating it can workaround this. 

But how do I fix  this problem?

[BD 41-237] Bus Interface property FREQ_HZ does not match between /system_ila_0/SLOT_0_AXIS_TLM(100000000) and /axis_counter_0/M_AXIS(125000000)

since the FREQ_HZ property is read only. 

I feel I did get it to work the first time I instantiated it in the project but now it just does not associate with the correct clock. 

Any pointers appreciated. 

 

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ggillett
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Registered: ‎08-14-2018

The TLM interface seems to cause the problems.Using RTL It has not crashed when changing the IPs configuration and FREQ_HZ is correctly set.

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ggillett
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Registered: ‎08-14-2018

The TLM interface seems to cause the problems.Using RTL It has not crashed when changing the IPs configuration and FREQ_HZ is correctly set.

View solution in original post

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ggillett
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Registered: ‎08-14-2018

I accepted my own solution to soon, it did crash again on reconfig. Upon reopening the project I could finish the reconfig without a crash. After rerunning generate bitstream I noticed that both synth and implementation where out of date even though they just had just been run, rerunning generate bitstream allowed the hardware to be exported. This core really is a PITA.

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