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Registered: ‎10-16-2010

using reset value as an initial register value for Vivado

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 Hello,

 

When I am synthesizing the code below in ISE, the initial value of the register reg1 is 5 (although I don't press the reset button). Now, I am synthesizing the same code in Vivado, the initial value of the register reg1 is 0.

 

always @ (posedge clk)
begin
  if( rst )
         reg1 <= 5;
  else
         reg1 <= data;
end

 

I know, I can give initial value while decleration of reg1 as:

 

reg [2:0] reg1 = 3'd5; //(I didnt need this for ISE)

 

But I have a long code and I dont want to initialize every register one by one. Is it possible to make the same register initialization of ISE for Vivado ?  Or, can you please explain me where the difference comes from ? 

 

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Participant
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Registered: ‎10-16-2010

Re: using reset value as an initial register value for Vivado

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Hello, I found that the problem was related with ucf file for reset signal, now it works with correct assignment. Somehow my reset signal was floating and Vivado was not initializing the registers with reset case statement since reset signal is not connected. I am sorry for taking your time, and thank you for your helps.    

 

 

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Moderator
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Registered: ‎07-01-2015

Re: using reset value as an initial register value for Vivado

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Hi @kadirakin85,

 

You can initialize all the registers after performing synthesis. Please follow the below steps:

Run the synthesis.

·         Open the synthesized design then use the TCL command through TCL console.

·         set_property INIT <value>[all_registers]

For example if you want to initialize all the registers to logic 1 then you can use TCL command

set_property INIT 1'b1 [all_registers ].

 

Hope the above steps helps.

 

Thanks,
Arpan

Thanks,
Arpan
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Participant
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Registered: ‎10-16-2010

Re: using reset value as an initial register value for Vivado

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Hello,

 

Thank you, but Initial values of all my registers are different.. I want to initialize my registers with the reset case assignments (without pushing reset button). This was working in ISE (as I wrote above). Is there any TCL command that initializes all registers with respective reset case values, or any other solution ? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: using reset value as an initial register value for Vivado

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Hi @kadirakin85

 

The initial value can be specified along with the signal declaration as below.

    reg reg_name=1'b0;

    signal  signal_name : std_logic := '0';

 

 

When there's no initial value specified with the signal declaration, the INIT value is determined by reset value. That's to say, the INIT value of FDRE and FDCE is 0, and the INIT value of FDSE and FDPE is 1.

 

    For example, Vivado Synthesis infers an FDSE with INIT value set to 1'b1 from the following code 

 

    reg dout;    
    always @ (posedge clk)
    if(rst)
    dout <= 1'b1;
    else
    dout <= din;

 

Note: When there is initial value specified with the signal declaration but different from the reset value, the former takes priority over the latter.

 

When there's no initial value specified with the signal declaration and no reset is used, the INIT value is 0.

 

Are you assiging intial value during signal declaration by any chance?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Registered: ‎10-16-2010

Re: using reset value as an initial register value for Vivado

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Thanks Vemulad,

 

As I wrote, I am using the same code for ISE and Vivado. If I was using initialization, this could be a problematic case for ISE too, but ISE initializes registers with reset case values.

 

But anyway, I am sure that I dont make any initialization in my verilog codes except using reset. If there is a special setting in Vivado to handle this issue, or if Vivado automatically uses any tcl, I don't know where they are or I dont know how can I modify them. I just checked Tools -> Project Settings, then tcl.pre and tcl.post directories for synthesis and implementation seem empty.

I think the difference between ISE and Vivado on this issue may be related with global reset (GSR). I read somewhere that ISE configures registers by appying global reset (GSR) while the configuration of the FPGA, but this is not the case for Vivado (to reduce hardware resource consumption since GSR needs another path for itself). I don't know if this information about Vivado is true or not (GSR doesnt apply automatically in Vivado). If this is true, how can I change the settings of Vivado to apply GSR (if this is what I need) ?  

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Participant
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Registered: ‎10-16-2010

Re: using reset value as an initial register value for Vivado

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Hello, I found that the problem was related with ucf file for reset signal, now it works with correct assignment. Somehow my reset signal was floating and Vivado was not initializing the registers with reset case statement since reset signal is not connected. I am sorry for taking your time, and thank you for your helps.    

 

 

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