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Visitor nihi
Visitor
8,986 Views
Registered: ‎11-26-2014

vhdl coding problem

Hello

 

I have to replicate this logic 9 times and I applied generate statement
in component instantiation, it is not showing any error in syntax but
not giving any output showing uuuuuuuuuuuuuu. I am attaching that code .
please help me out urgently.
where:  roundtkey,roundkey1,cypher,cypher1(0th round output) ,cypher2
are 128 bits.
         and i is for round. we need round only in key generation. we
have to replicate same steps for 9 rounds and each round's output will
go to other round's byte substitution step.

 

Thank you

code.JPG
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3 Replies
Xilinx Employee
Xilinx Employee
8,973 Views
Registered: ‎10-24-2013

Re: vhdl coding problem

Hi,

Is it possible to attach the complete code and the testbench?
Thanks,Vijay
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Visitor nihi
Visitor
8,963 Views
Registered: ‎11-26-2014

Re: vhdl coding problem

Hiiiii

I am attaching the whole code with its package code file.

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Xilinx Employee
Xilinx Employee
8,939 Views
Registered: ‎10-24-2013

Re: vhdl coding problem

Hi,
Thanks for the files. Let me check and get back to you.
Thanks,Vijay
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