creating an IP block in Vivado 2018.2, in thi scase video frame buffer read
takes some time to generate out of context,
so click to put it into background.
want to start looking at the next IP whilst waiting,
in this case the rgb to YCrCb,
so select the RGB IP, and click on the IP properties, change log, view change log.
get error saying , can't look at the log due to back gound task running...
Dah, I'd have thought chanage log is just a text file,
it looks like it when the background process for the other IP has stopped,
why can't I open the change log whilst a background IP is running !
Ok, not something I want to do often,
but multi tasking is the way of the world,
We now have Vivado 2018.2 up from the days of ISE 14.7, but has the sim speed of ISIM changed (I consider this a very fundamental necessity)?
Then this is just a trivial thing, which I am sure Xilinx is not going to pay proper attention.
Given the fact that Xilinx makes money by selling chips not their Vivado s/w!
------------FPGA enthusiast------------Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem