11-22-2019 09:42 AM
While I'm doing uart communication on a board,in my program I wire a "rx_done"signal which measn the fpga receives a byte sucessfully, it will cause a positive edge.And in other modules,I use "rx_done”as a sentitive singal in an always struct.
Smulation is ok,but on the board it dosen't work,so I want to ask how I can constraint "rx_done" like a clock wire,is this the solution to this problem?
11-22-2019 10:10 AM - edited 11-22-2019 11:02 AM
Sounds like Vivado synthesis is optimizing the signal away. Are you routing this signal to a top-level I/O port? That should preserve that net from being optimized away during synthesis.
You can also preserve the net by providing appropriate constraints. Refer to the section "Creating Synthesis Constraints" in UG949.
11-22-2019 11:19 AM