cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
265 Views
Registered: ‎04-11-2019

vivado verilog wire problem

While I'm doing uart communication on a board,in my program I wire a "rx_done"signal  which measn the fpga receives a byte sucessfully, it will cause a positive edge.And in other modules,I use "rx_done”as a sentitive singal in an always struct.

Smulation is ok,but on the board it dosen't work,so I want to ask how I can constraint "rx_done" like a clock wire,is this the solution to this problem? 

0 Kudos
2 Replies
Highlighted
Contributor
Contributor
256 Views
Registered: ‎12-11-2007

Re: vivado verilog wire problem

Sounds like Vivado synthesis is optimizing the signal away.  Are you routing this signal to a top-level I/O port?  That should preserve that net from being optimized away during synthesis.

You can also preserve the net by providing appropriate constraints.  Refer to the section "Creating Synthesis Constraints" in UG949.

0 Kudos
Highlighted
Teacher
Teacher
219 Views
Registered: ‎07-09-2009

Re: vivado verilog wire problem

why do you think this signal is the problem in the real system ? Even if it does not happen in the real chip that is not likely to be because the tools are chucking it away,

General debug questions,

What is the chip, OS and versions your using ?

Can you post your constraints as an attachment please ?
Can you post your code as an attachment please ?


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos