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12,719 Views
Registered: ‎06-04-2014

waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

hello all,

 

i'm working on kintex 7 board. and i'm using chipscope pro for debugging my code. my design is consisting of three asynchronous clocks. using clocking wizard i generated three clocks which are of 20Mhz, 100Mhz and 800Mhz. i have given 20Mhz as the clock to the ila and vio clocks. But upon "analyse design using chipscope" i could not able to see the waveforms!

for the very first time, i could see sample buffer is full, but upon triggering no change in the waveform. Again when i did some modifications to the code without altering the constraints, i could not able to see the "sample buffer is full"..

 

Is .cdc file is a must when going for chipscope?? 

 

 

thanks in advance

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23 Replies
Xilinx Employee
Xilinx Employee
12,714 Views
Registered: ‎04-16-2012

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hi,

.cdc file is required if you are using core inserter flow.
.cdc file is not required if you are using core generator flow.

 

For difference in core inserter and core generator flow, see this user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/chipscope_pro_sw_cores_ug029.pdf

Thanks,
Vinay

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Moderator
Moderator
12,703 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

As per your description I came to know that you are using 20 MHZ clock as ILA clock (i.e. Nothing but your sampling clock).

And you are able to see the signals in waveform windows but the signals are constanat 1 or 0.

Please correct me if my understanding is wrong.

 

If my understanding is correct.

I have few questions for you:

1) What is your design clock (Clock used by your sequential logic)? Is it 20 MHZ or something different?

--> If its 20 MHZ (i.e. If your design clock is same as your sampling clock) then the behaviour you are facing is not an issue.

--> Sampling clock should be twice the design clock.

Please refer this link: http://www.xilinx.com/support/answers/18667.html

 

Thanks,

Yash   

12,700 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

thank you for your valuable response yash!

my design clock is 20Mhz, and one of the module will be working @ 100Mhz and 800Mhz clocks in the design

I have generated the three clocks from the system clock. 

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Xilinx Employee
Xilinx Employee
12,698 Views
Registered: ‎10-24-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hi,
Moving to Design Tools - Others board.
Thanks,Vijay
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Moderator
Moderator
12,697 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

The ILA you are using which capture the data probe of design which works on 20MHz?

If yes, then you have to use sampling clock of 40 Mhz. {Twice the design clock}.

 

Thanks,

Yash

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12,692 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

yes, right now im using the sampling clock as twice the design clock and i'm able to observe that my design is taking the clock.. but upon giving the necessary inputs, could not able to obtain the 18 bit data as output.. though my simulation is working correctly.. unable to figure out where the problem is?
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Moderator
Moderator
12,688 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Ok, from your last post it concluded that you are able to see signals on waveform windows. Right?

But you are unable to see expected output corresponding to the input signals?

 

I have question here for you:

1) Which simulation you are refering? Is it RTL or Functional simulation? Post-synthesis simulation? or Post-Implementation Simulation?

 

If you are refering to RTL or functional simulation then please check for post-Implementation simulation.

 

Thanks,

Yash

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12,685 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

yes yash! im done with the functional simulation.. i think i have an issue with the reset input.. when it is made low, the outputs are low. when reset is made high, i need to get the desired output. but this is not happening..
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Moderator
Moderator
12,684 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

I recommended you to see the functionality in post-implementation simulation.

Functional simulation is nothing but an RTL representation of the design. Post-implementation simulation represent the hardware behaviour of your design.

 

1st check the post-synthesis simulation and compare with functional simulation. If it's correct then go for post-implementation simulation and again comapre with functional simulation.

 

If there is issue in post-synthesis simulation check if there are any warnings related to the signal you are looking for.

 

Please try above suggestion only this way you can debug the issue and find out the root cause.

 

Thanks,

Yash

Moderator
Moderator
12,088 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Is your issue resolved now?

If yes, please close this thread by accepting post as answer which was helpful to you.

 

If you have query post it back.

 

Thanks,

Yash

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12,086 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

No, yash! still functional simulation and post synthesis simulation are to be compared..  as you mentioned yesterday.

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Moderator
Moderator
12,082 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Is your post-synthesis simulation and RTL/functional simulation results are expected and matching each other?

 

If yes, what about post-placeandroute (Post-implemenation) simulation?

 

Thanks,

Yash

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12,074 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

yes yash! post-synthesis simulation and RTL simulations are matching eachother perfectly! but in post implementation simulation im not able to obtain the output..

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Moderator
Moderator
12,052 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

So now we come to know that issue is in Implementation of design.

Please check all warnings in Implementation phase. Also check if there is any trimming of signals or FF happened during optimization phase. If you are facing any trimming of signal which was related to your output signal add attribute to save the signals from trimming.

 

Thanks,

Yash

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12,050 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

yes yash! most of the warnings are like "signals get trimmed " and the blocks are unconnected in the module....making sure to make all those warnings done

 

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Moderator
Moderator
12,048 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Hey i guess you got the clue :)

Please fix those warnings and i hope it will be working fine :)

 

Post if you have any doubt or issue. 

 

Thanks,

Yash

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12,042 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

hello yash!!

 

unable to resolve the following warning:

WARNING:Xst:2677 - Node <DATA_OUT_15> of sequential type is unconnected in block <STP1>.

 

though i'm done with the necessary corrections , unable to obtain the post-translate simulation..

 

can you please help me in this!!

 

 

 

 

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Moderator
Moderator
12,039 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

XST: 2677 - This warning indicates that the sequential signal in the block is unconnected and will be removed. This is a common warning during Synthesis optimization. It does not always indicate a coding error. If the Post-Synthesis/Translate simulation shows the design functions correctly, you can safely ignore this warning. 

If this signal is not expected to be unconnected or removed, check if the downstream loads of this signal are correctly connected. To prevent this signal from being removed, add KEEP and S (Save Net Flag) constraints to it. For the syntax of the constraints, please refer to Constraints Guide.

 

Try this also:

If register is absorbed by the block, set Keep Hierarchy option to Yes will remove this warning mesage. 

 

Thanks,

Yash

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12,037 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

thank you for your reply yash! i'm done with that warning now. and i came to understand that post route simulation is failing because of the memories in my design.

 

actually my design consists of memories ranging from [0:511]... upon mapping the design, im getting these warnings regarding the memories.

 

WARNING:HDLCompiler:1007 - "N:/P.40xd/rtf/verilog/src/simprims/X_RAMB36E1.v" Line 1936: Element index 4 into memp is out of bounds
WARNING:HDLCompiler:1007 - "N:/P.40xd/rtf/verilog/src/simprims/X_RAMB36E1.v" Line 1940: Element index 5 into memp is out of bounds
WARNING:HDLCompiler:1007 - "N:/P.40xd/rtf/verilog/src/simprims/X_RAMB36E1.v" Line 1944: Element index 6 into memp is out of bounds
WARNING:HDLCompiler:1007 - "N:/P.40xd/rtf/verilog/src/simprims/X_RAMB36E1.v" Line 1948: Element index 7 into memp is out of bounds

 

is there any possibility to ignore these warnings to proceed further? yash!

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Moderator
Moderator
9,484 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Please refer this AR: http://www.xilinx.com/support/answers/38216.html 

 

Size mismatch during mapping can cause this issue and lead to simulation mismatch.

 

Thanks,

Yash

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9,471 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

hello yash! now besides the warnings after post map simulation, im able to obtain the output but i could able to figure out there is a frequent change in the data into two registers.

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Moderator
Moderator
9,469 Views
Registered: ‎01-16-2013

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

Hello samiyuktha@kalalii ,

 

Could you please elaborate your query?

I am unable to understand what's the issue now you are facing.

 

Thanks,

Yash

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9,466 Views
Registered: ‎06-04-2014

Re: waiting for core to be armed.. even every thing is fine and the code is synthesized using chipscope

sorry for the confusion i made in elaborating the query.

 

during the post-map simulation, i'm getting some unwanted results prior to the completion of the actual output. the result of this is im able to get some false data as output before the expected one..

 

im attaching the post-map simulated window in this for your analysis.. 

please consider

debug.png
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