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jspangar
Observer
Observer
13,254 Views
Registered: ‎12-26-2013

xpower read_vcd fails due to invalid vcd syntax (Error Power 33-36) ncsim simulator vcd output

I am attempting to annotate Xpower with VCD dump output from Cadence Incisive Enterprise Simulator (IES) NCSIM based on a verilog design. The simulation runs fine and passes all vectors using backannotated sdf files on an implementation built on a 980T FPGA. The simulation is set up to generate a VCD dump output to a file. I can read the VCD file into the simvision waveform viewer just fine so the VCD file seems OK, albeit a couple of gigabytes.

 

I am attemptin to read the VCD annotation into Vivado against the implemented design using the read_vcd command in order to annotate activity factors for accurate power analysis.

 

However when doing to read_vcd command, the tcl read_vcd command persistently issues a read_vcd error as per the output below:

 

 

-------------------------------------------------------------------------------------  error log ---------------------------

 

read_vcd -verbose dec_sp_top_wrapper.vcd
INFO: [Power 33-168] Parsing VCD file dec_sp_top_wrapper.vcd
ERROR: [Power 33-36] Invalid syntax encountered while parsing VCD file: line 932410: no identifier code was specified for binary value change.
Resolution: Regenerate VCD file, supply it to Vivado and rerun report power. If the error persists, please visit http://www.xilinx.com/support
ERROR: [Power 33-36] Invalid syntax encountered while parsing VCD file: line 932411: no identifier code was specified for binary value change.
Resolution: Regenerate VCD file, supply it to Vivado and rerun report power. If the error persists, please visit http://www.xilinx.com/support
ERROR: [Power 33-36] Invalid syntax encountered while parsing VCD file: line 932412: no identifier code was specified for binary value change.
Resolution: Regenerate VCD file, supply it to Vivado and rerun report power. If the error persists, please visit http://www.xilinx.com/support
ERROR: [Power 33-36] Invalid syntax encountered while parsing VCD file: line 932421: no identifier code was specified for binary value change.
Resolution: Regenerate VCD file, supply it to Vivado and rerun report power. If the error persists, please visit http://www.xilinx.com/support
INFO: [Power 33-9] VCDFile(270760253): $dumpoff command encountered, all simulation data after this will be ignored.
INFO: [Power 33-26] Design nets matched = 32301 of 32301
INFO: [Power 33-178] VCD annotation done from file dec_sp_top_wrapper.vcd
read_vcd: Time (s): cpu = 00:05:46 ; elapsed = 00:05:37 . Memory (MB): peak = 6852.086 ; gain = 399.035
ERROR: [Common 17-39] 'read_vcd' failed due to earlier errors.

--------------------------------------end of error log -----------------------------------------------------------------------

 

 

I have examined the vcd file manually and there is nothing at all remarkable about the lines identified in the error log:

 

932400 x4[,
932401 x5[,
932402 x6[,
932403 x7[,
932404 x8[,
932405 x9[,
932406 x:[,
932407 x;[,
932408 bx <[,
932409 bx =[,
932410 x>[,
932411 bx ?[,
932412 bx @[,
932413 xB[,
932414 xC[,
932415 xD[,
932416 xE[,
932417 xF[,
932418 xG[,
932419 xH[,
932420 xI[,
932421 xJ[,
932422 bx K[,
932423 bx L[,
932424 xM[,
932425 bx N[,
932426 bx O[,
932427 xQ[,

 

For example, comparing the signals identified in line 932409 (which it does not complain about) with the signals in line 932410 (which it does complain about) they both look equally fine:

 

(signal from line 932409)

bash-3.2$  nl dec_sp_top_wrapper.vcd | fgrep -e "=[,"
188363 $var reg       3 =[,  s [2:0] $end
932409 bx =[,
1362567 bx0x =[,
42917617 bx0x =[,
270828957 bx =[,

 

(signal from line 932410)

bash-3.2$  nl dec_sp_top_wrapper.vcd | fgrep -e ">[,"
188366 $var reg       1 >[,  lut4_mux4  $end
932410 x>[,
42917618 x>[,
270828958 x>[,
bash-3.2$

 

 

I have regenerated the VCD file several times, including changing the dump on and off points to shrink the file size down to see if that helps. The exact same error is issued each time, no more, no less.

 

The result is that xpower fails completely, and it is not possible to obtain an accurate transition-based power analysis from vcd for this design. Any assistance greatly appreciated.

 

I am using vivado 2013.3 64-bit, but may try upgrading to the recently released 2013.4 in the hope that it fixes it.

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7 Replies
siktap
Scholar
Scholar
13,243 Views
Registered: ‎06-14-2012

Can you give a try by using the "-f" switch to flatten buses (vectors)?

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ksubram
Xilinx Employee
Xilinx Employee
13,236 Views
Registered: ‎10-28-2013

Hi

 

We recommend to you SAIF instead of VCD.

You can convert your existing VCD to SAIF using 'vcd2saif' utility (it comes with Synopsys tools).

 

Else, please dump SAIF format directly from NCSim and use it with:

   read_saif -file dump.saif

 

How to dump saif in NCSim:

                NCSIM uses ‘dumpsaif’ command which is similar to ‘dumpvars’.

                          Specify the scope to be dumped and the output saif file name

                                    dumpsaif –scope hdl_objects –output filename.saif

 

                         Run the simulation

                       End the SAIF dumping

                            dumpsaif –end

 

For more detailed usage or information about each commands, please refer the NCSIM User Guide.

                Example Tcl command file:

                                dumpsaif –scope /tb/fpga/* -output routed.saif

                                run 500ns

                                dumpsaif –end

                                quit

This should work and the right solution/use model for Power Nalysis.

 

Btw, the new Power Tool is called Vivado Report_Power (no more called XPower which is part of ISE Tool).

 

Thanks,

Karthik

 

Regards,
Karthik
Power Analysis & Optimization
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debrajr
Moderator
Moderator
13,187 Views
Registered: ‎04-17-2011

@jspangar Is the issue solved for you? If yes, feel free to mark the post which helped you the most as an Accepted Solution. It is a good forums practice.

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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jspangar
Observer
Observer
13,182 Views
Registered: ‎12-26-2013

As I do not have access to vcd2saif the option of converting my original VCD file was not available to me.

 

So instead I set up my simulation to dump SAIF output. This is a bit more fiddly because I have to stop the simulation and issue the TCL commands to dump SAIF but the SAIF files are significantly smaller - some of the VCD files were tens of gigabytes.

 

The other hassle is that simvision which I am using to view the outputs does not read SAIF format so I had to dump both the VCD and the SAIF files (I dumped them from the same points in time) so I could look at what had been dumped by reading the VCD into simvision but read the SAIF file in to get switching activity for power analysis.

 

The SAIF file appeared to be read in with the read_saif command successfully. 100% of nets were matched, which is a good sign. So as far as fixing my original problem goes this worked as a solution. However I then hit another problem, in that the clock constraint showed in the power report gave a clock period of about 300 times the actual clock period in the simulation, and also changing the clock period by a factor of two resulted in only about a 3% varation in dynamic power reported. This problem has been mostly reported in my next posting. I am still waiting for an answer to that posting.

 

As an update, after many experiments without a better result to the clock constraint problem, I upgraded from 2013.3. to 2013.4 and lo and behold all of a sudden power_analyzer is reporting the correct clock constraint! So I can only surmise that there was a bug and it was fixed. At the same time, now not 100% of nets are matched, so I will try and write_vcd and write_sdf again from the new install and see if that improves it. Also the dynamic power went down a bit, although as reported before I don't have much confidence in the dynamic power report if it is largely independent of clock frequency.

 

I'd appreciate a response to my other posting sometime if possible, and if possible an explanation as to why doubling the clock period would make almost no difference to dynamic power.

 

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jspangar
Observer
Observer
13,180 Views
Registered: ‎12-26-2013

>  so I will try and write_vcd and write_sdf again

 

Oops, I meant write_verilog. Mondayitis.

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ksubram
Xilinx Employee
Xilinx Employee
13,176 Views
Registered: ‎10-28-2013

Hi

 

I think you are on right path - exploring the Power Analysis usage.

 

You should be able see the expected power numbers with:

      new SAIF generated on current routed netlist.

 

How are you changing the frequency - doubling?

           through XDC commands? - create_clock ....

           using Power Tcl command? - set_switching_activity

 

   In any case, you should be able see the right power numbers, provided that the control signals are set correct activity rates.

 

Agian, I would request the same : share the .dcp & saif, if you like us to look at it once to coverge on this quickly.

 

   

Regards,
Karthik
Power Analysis & Optimization
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jspangar
Observer
Observer
13,173 Views
Registered: ‎12-26-2013

Hi Karthik,

 

Well I seem to have solved one problem by upgrading and created another.

 

The problem I solved was the clock constraint reported in the power analysis. Instead of being 12ns it was the below:

 

2.2 Clock Constraints

---------------------

 

+---------+---------+-----------------+

| Clock   | Domain  | Constraint (ns) |

+---------+---------+-----------------+

| clk_dec | clk_dec |          3471.8 |

+---------+---------+-----------------+

 

Now, immediately after upgrading to 2012.4 I get this instead:

 

2.2 Clock Constraints

---------------------

 

+-------------------+-------------------+-----------------+

| Clock             | Domain            | Constraint (ns) |

+-------------------+-------------------+-----------------+

| clk_dec           | clk_dec           |            12.0 |

| clk_dec_IBUF      | clk_dec_IBUF      |            12.0 |

| clk_dec_IBUF_BUFG | clk_dec_IBUF_BUFG |            12.0 |

+-------------------+-------------------+-----------------+

 

Very nice.

 

However, previously when I did read_saif it happily matched 100% of design nets. When I simply upgraded and did read_saif there were just under 1000 nets not matched. I guess from the quantum these might have been I/O pads but don't know for sure. So, I thought well I'd better go back and redo the synthesis and P&R because who knows what might have changed when upgrading the database. I did this (see below), but the SAIF results still do not match 100% of nodes. This seems wrong.

 

I noticed my power reports went down quite a bit (< 10%) when I upgraded to 2012.4 but do not have a good reason for that observation. Power reports going down and nets missing from the SAIF activity report annotation does not supply the requisite warm and fuzzies though.

 

The only thing I have not tried is recompile the whole thing from RTL, but I'm guessing it will not help.

 

To answer your questions:

 

How are you changing the frequency - doubling?

           through XDC commands? - create_clock ....

           using Power Tcl command? - set_switching_activity

 

   In any case, you should be able see the right power numbers, provided that the control signals are set correct activity rates.

 

Well, the clock frequency is changed in my verilog testbench by changing the speed of the testbench clock used for the simulation. Everything else follows the clock of course.  I'm guessing here, but I thought the clock node activity would be derived from the SAIF file (that would be a reliable way to do it) but who knows maybe the tool takes a short cut and just assumes the clock frequency from the synthesis constraint. That would be a dumb way to do it if you ask me because there is nothing to say the synthesis constraint will always be made the same as what the testbench generates (like in my case) but then I'm not an EDA designer. A bit of documentation to explain what it is reporting would be helpful though.

 

I do have another post in this forum where I am trying to find out what happens if a window of simulation of a SAIF file is passed to the power analyser tool but nobody has answered that one yet.

 

Agian, I would request the same : share the .dcp & saif, if you like us to look at it once to coverge on this quickly.

 

I would be happy to do this but not in this forum. If you could please email me offline with instructions how to send you these files I will do so. They are largish.

 

Thanks

- Justin

 

 

reset_run synth_1
reset_run: Time (s): cpu = 00:00:21 ; elapsed = 00:00:06 . Memory (MB): peak = 6723.891 ; gain = 0.000
launch_runs synth_1
[Sun Jan 12 20:47:52 2014] Launched synth_1...
Run output will be captured here: /work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/test_design_xfpga.runs/synth_1/runme.log
launch_runs impl_2
[Sun Jan 12 20:58:38 2014] Launched impl_2...
Run output will be captured here: /work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/test_design_xfpga.runs/impl_2/runme.log
refresh_design
INFO: [Netlist 29-17] Analyzing 785 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Parsing XDC File [/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/.Xil/Vivado-31298-compserv4.xxx.com/dcp/test_des_top_wrapper.xdc]
INFO: [Vivado 12-2286] Implicit search of objects for pattern 'clk_dec' matched to 'clock' objects. [/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/test_design_xfpga.srcs/constrs_2/new/test_des_top_wrapper.xdc:2]
Resolution: To avoid ambiguous patterns, provide proper objects using get commands e.g. [get_nets xyz].
INFO: [Timing 38-35] Done setting XDC timing constraints. [/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/test_design_xfpga.srcs/constrs_2/new/test_des_top_wrapper.xdc:851]
set_load: Time (s): cpu = 00:00:35 ; elapsed = 00:00:18 . Memory (MB): peak = 6723.891 ; gain = 0.000
Finished Parsing XDC File [/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/.Xil/Vivado-31298-compserv4.xxx.com/dcp/test_des_top_wrapper.xdc]
Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6723.891 ; gain = 0.000
Restoring placement.
Restored 7120 out of 7120 XDEF sites from archive | CPU: 6.360000 secs | Memory: 50.412880 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files:
refresh_design: Time (s): cpu = 00:02:32 ; elapsed = 00:00:56 . Memory (MB): peak = 6745.395 ; gain = 21.504
write_verilog decoder_sp_tb_time_impl.v
write_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 6745.395 ; gain = 0.000
/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/decoder_sp_tb_time_impl.v
write_sdf decoder_sp_tb_time_impl.sdf
write_sdf: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 6745.395 ; gain = 0.000
/work/justin/design/test_design_fpga/design/vivado/test_design_xfpga/decoder_sp_tb_time_impl.sdf
read_saif test_des_top_wrapper.saif
INFO: [Power 33-167] Parsing SAIF file test_des_top_wrapper.saif
INFO: [Power 33-26] Design nets matched = 33595 of 34444
INFO: [Power 33-177] SAIF annotation done from file test_des_top_wrapper.saif
read_saif: Time (s): cpu = 00:01:13 ; elapsed = 00:00:43 . Memory (MB): peak = 6773.395 ; gain = 28.000
test_des_top_wrapper.saif

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