09-25-2012 11:09 AM
I am using ISE 11.1. I was just going through xpower analyzer. In this contrast I got zero logic power for a specific algorithm. Here I have few query
1) Is it possible to have zero logic power.
2) Which power is expensing as logic power.
09-25-2012 11:38 AM
There is no such thing as zero power.
There is the static power.
There is the dynamic power.
For slow clock rates (i.e. less than a Megahertz), dynamic power may be so low, that it is effectively masked by the static power. In such cases, the dynamic power may appear to be zero.
09-25-2012 11:46 AM
09-25-2012 12:02 PM
actually the dynamic power is the summation of few powers, like clock power, signal power, logic power, IO power etc.
Are these terms which you have defined, or are these terms defined and itemised by the ISE 11 power analysis tool? If these are your terms and definitions, it would be helpful to describe them a bit more clearly. It has been too long since last using the ISE 11 toolset, so your indulgence in answering these questions is appreciated.
In that case I have got logic power=0. Is it possible to have 0 logic power for a particular design.
I would suppose that the answer depends -- at least in part -- on the accepted definition of "logic power".
-- Bob Elkind
09-25-2012 12:38 PM
09-25-2012 12:53 PM
Hopefully all are not about humiliation, Im really grateful to such kind of your experienced personality, and obviously I am looking forward to u.
I appreciate the interest you have in learning. There are useful reasons I asked certain questions in my previous post, and I am puzzled that you -- as a research trainee interested in useful exchange of ideas -- did not answer one of these questions. Here is the question you did not answer:
Are these terms which you have defined, or are these terms defined and itemised by the ISE 11 power analysis tool?
I ask this question for the following reason: to understand whether helping you with the ISE toolset is useful to you, or whether helping you with fundamentals of logic circuits is helpful to you.
If you are interested in help with the ISE toolset, please consider updating to a more current version of the software (Xilinx has released version 14.2, as this is being written). Very few designers remember ISE 11 well enough to offer useful and specific answers to your questions.
-- Bob Elkind
09-25-2012 01:10 PM - edited 09-25-2012 01:17 PM
Updating the ISE software to 14.2 from 11 has nothing to do with the basics of understanding the very few basic definitions(actually the dynamic power is the summation of few powers, like clock power, signal power, logic power, IO power) of Rourab Paul(Research Trainee) which can be found in basic electronics book and is expected to know even from a beginner in electronics. So I am really schoked by the reply of an expert contributor who has claimed to have been puzzled (actually forgot) the basic understandings and openly criticising and discouraging the concept of exchanging useful ideas by the young scientists of today...
09-25-2012 01:19 PM
I do not think anyone is discouraging questions on this forum.
Rather, I think we are trying to understand the question.
Often, so little resource is used, or such a low frequency clock is used, that power estimation of a design is exactly the same as no design at all (static power dominates).
This was my first post.
Now we wish to find out what tool(s) (power estimator, power analyzer) were used, what areas had power, what was the frequency, and the toggle rates, etc. etc. etc.
As to what the status of the forum author is (expert, super, etc.) I pay very little attention to that, as often these foum tools are just counting how often one posts, and has no idea of the quality of the posts themselves.
More interesting is the rating of the various authors: if they are in the top five, then the community at large thinks they are the helpful ones, as opposed to anyone else.
I am very happy to let the users vote. After all, they are my customers. If I do not make them happy, then I should change my ways.
09-25-2012 01:36 PM - edited 09-25-2012 03:13 PM
Chandrajit and Rourab Paul,
Chandrajit, if you understand Rourab's questions, it would be helpful to Rourab if you are able to answer Rourab's posts.
If Rourab's questions are unrelated to ISE software, then this should be made clear from the beginning of this thread.
As a design engineer, I try to be sure that my understanding of a question is correct before I compose an answer to the question, to avoid misleading or confusing answers. I am confident that both of you can appreciate the value of clear understanding and communication in technical discussions.
Apparently we are each guilty of misunderstanding. Chandrajit and Rourab misunderstand the intent of my questions and responses, and I misunderstand Rourab's questions and their relation to Xilinx products and software.
-- Bob Elkind
09-26-2012 09:11 AM
This thread seems to be quite interesting..lots of discussion among a xilinx employee,a super contributor,a regular contributor, and an expert contributor..But is there any contribution ultimately on the basic problem?,which has been asked at begining...
Rourab paul if u found ur ans then mark it any of these as soln otherwise let it be continued untill there is no ultimate soln....
09-26-2012 10:39 AM
I would like to pay attention to my queries. I am confused with logic power because I could not understand the dynamic power related to logic operations. All of the logic toggling should update the data bits finally which should be considered as signal or IO power. Is there any intermediate register which holds the intermediate values during the logical operations? Is that power considered as Logic power?Hopefully I can clear my confusions.
Thank u for sharing your appreciations
“If Rourab's questions are unrelated to ISE software, then this should be made clear from the beginning of this thread.”
I am not getting u. Is my question unrelated to ISE ?
“As a design engineer, I try to be sure that my understanding of a question is correct before I compose an answer to the question, to avoid misleading or confusing answers. ”
Obviously you can do and apparently I am also guilty that I could not express my queries clearly. I hoped the clear cut, straight, direct question would be understandable easily and can save your valuable time consumption, and that’s why I asked my crisis directly. I could not understand that before posting my question I need to describe all of my initial understanding regarding my specific query.
09-26-2012 10:50 AM
What tool are you using?
XPE or XPA?
With no registers at the output of your logic, you will get 0 power.
Only synchronous (clocked) design is supported.
09-26-2012 10:58 AM - edited 09-26-2012 10:58 AM
Once you have a clock,
Then the tools will understand toggle rates (either guessed at in XPE, or in a .vcd file in XPA, or the default 50% with no .vcd in XPA).
Logic power, including a glitch power (from different arrival times at LUT causing glitches in the output of the LUT) is then calculated accurately (in XPA).
XPE is given a toggle rate by you, along with the clock, and makes a good guess at the power.
XPA is more accurate than XPE. Both are only as good as hte design and information you give them.
If you give them garbage, you get garbage.
Logic all by itself is of no interest to commercial customers (as we only support synchronous sytem design). But the power in that logic, is calculated once the tools understand it is part of a synchronosu system.
09-26-2012 11:04 AM
09-26-2012 11:08 AM
09-26-2012 11:23 AM
Is this a synchronous design?
If you use the default (50% toggling of all inputs), you should get consistent results.
Version 9 is ancient now. I imagine we were still trying to improve XPA substantially way back then.
Perhaps you could upgrade to something more recent?
What part are you targeting? Perhaps this is why you can not upgrade to a newer version? I understand the Virtex II Pro is still out there, and being used (by students, etc.) but there are no new designs happening with that ancient family, and it is not recommended for use (now).
It may be very difficult to estimate power on really old parts. It would be faster to build a bitstream, and measure the power.
Is there any reason why you do not answer the questions when they are directly stated to you? Is this a secret program? If so, just say "I can not answer your questions...."
It is very hard for us to guess what your problem is.
Is the design something you could actually post here (verilog or VHDL)?
10-11-2012 08:11 PM
10-12-2012 07:18 AM
The feature of time based power was not at all "real", nor accurate.
For that to really work, it needs the schematics of the FPGA device (or massive characterization).
10-12-2012 07:58 PM
I am not getting this line "it needs the schematics of the FPGA device (or massive characterization)."
Actually Austine I am working on power masking circuit which is very much related to side channel attack of cryptography.
In that case I want to know is there any other options to calculate more or less accurate power in time domain?
10-17-2012 12:55 AM