We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Configurable Reporting

by Xilinx Employee ‎10-26-2017 11:07 AM - edited ‎10-26-2017 11:12 AM (807 Views)

Configurable Reporting 

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 


Configurable reporting is a new Vivado project feature that allows you to run any report at any step of the flow.  For instance, let’s assume you have a critical path post implementation, and you are not sure how to address it.  To understand how this critical path “evolved” through the flow, configurable reporting will give you the ability to report timing on that exact path post opt design, post place design, post route design, and every step in between.  Figure 1 shows report timing summary added to each of the implementation flow steps.  Knowledge of the timing at each of these steps can help you understand if the problem is a synthesis issue, a utilization issue, a clock distribution issue, or a route congestion issue. 


Figure 1.  Report timing summary configured to run after three flow steps in the properties tab of an implementation run


Layered on top of configurable reports, we are also introducing the concept of report strategies.  Similar to how run strategies allow you to tailor the capabilities of Vivado to satisfy your unique requirements, report strategies allow you to tailor reporting to your design.  You can configure a report strategy and reuse it across runs or even across projects.  We are supplying several pre-configured strategies including: UltraFast methodology reports, performance explore reports, timing closure reports, or, if you prefer to simply run faster, you can choose the no reports option.  Figure 2 shows the tool settings window where a user can create their own custom strategy or view the Xilinx recommended strategies.  Figure 3 shows the design runs window with several implementation and synthesis runs configured with different run and report strategies.


Figure 2.  Tool settings window that allows the user to create their own custom strategies



Figure 3.  Design runs window showing several run and report strategies


Configurable reporting will give you the flexibility to decide which reports are most critical for your design and enable you to focus on solving your unique problems.  When you are in the final push to close your design, the only popping you’ll encounter are the corks celebrating your design completion.

About Author:
Brian Lay is a Sr. Product Marketing Manager for the Vivado IDE and supporting infrastructure.  As the IDE marketing manager he has been involved in many diverse projects at Xilinx including the timing constraints wizard, many new reports, project support for partial reconfiguration, and run-time hardware debug dashboards.  Brian holds a Master's degree in Electrical Engineering from the University of Illinois Urbana-Champaign and an undergraduate degree from the University of Minnesota.  He has over 17 years of experience and has worked at Sun Microsystems and Advanced Micro Devices.  His skills include full-custom circuit design, synthesis place and route, clock distribution design, full chip integration and all aspects of timing, noise, power, DRCs, IR drop to verify such circuits in CPUs, GPUs and FPGAs.

by Newbie @acersupport
on ‎02-14-2018 02:02 PM

I am having an error in figure 3.

Acer Tech Support

About the Author
  • Balachander Krishnamurthy is a Sr. Product Marketing Manager for SDSoC. His responsibilities include product planning, inbound and outbound marketing for Xilinx’s Vivado SDx Design Software. Bala holds a Master's degree in Electrical Engineering from San Jose State University. He has worked at Sun Microsystems and Altera for several years in multiple roles in verification, RTL design, first silicon and board bring-up and as an ASIC Product Manager. He has more than 17 years’ experience in the GPU, CPU, ASIC and FPGA industries. His current focus is FPGA methodology for synthesis, implementation and timing closure.
  • Sanjay is Senior Director, Software Validation, at Xilinx, where he and his team validate the company’s Vivado and SDx tool chains. For more than 20 years, Sanjay has worked in EDA and VLSI in India as well as in Silicon Valley in the United States. He has worked extensively on library characterization and modeling, HDLs (focusing more on Verilog than VHDL), simulation, synthesis, static timing analysis, power, clock domain crossing and synchronization, and rule checker-based verification. Sanjay has been learning Vivado in recent years. He has published three books as co-author and editor: Principles of VLSI RTL Design – A Practical Guide, Constraining Designs for Synthesis and Timing Analysis – Using Synopsys Design Constraints, and Designing with Xilinx FPGAs – Using Vivado. In addition, Sanjay has written numerous articles and papers for trade journals and conferences. He holds three patents related to clock gating and isolation cells. A resident of Hyderabad in India, Sanjay is a graduate of the India Institute of Technology Kharagpur in electronics and electrical communications engineering.