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Mismatch in Timing Numbers between SDF and STA

by Xilinx Employee ‎01-18-2018 12:11 PM - edited ‎01-19-2018 09:32 AM (801 Views)

Sometimes, we get situations reported, where the timing numbers for individual elements during Vivado STA do not match the timing numbers shown in the Simulation SDF file, also generated by Vivado.

This article tries to explain various possible reasons why this discrepancy might appear, and how to interpret/reconcile them.


Best way to download Xilinx Design Tools

by Xilinx Employee ‎12-19-2017 01:36 PM - edited ‎12-19-2017 02:00 PM (2,419 Views)

Have you ever noticed while streaming Netflix videos, sometime the video blurs and then returns to high quality very quickly? Do you know what Netflix did in-between those few seconds? Along with adaptive bitrate streaming, it is basically continuously scanning for best CDN(Content Delivery Network) servers that can deliver data-packets faster.

Netflix may have mastered this but techniques to deliver large amount of data without any interruption have been around for few years now. For example, at Xilinx, we have been using Web Installer with such features that enables faster downloads without any interruptions.


Configurable Reporting

by Xilinx Employee ‎10-26-2017 11:07 AM - edited ‎10-26-2017 11:12 AM (942 Views)

Configurable Reporting - Xilinx Marketing - Xilinx PPG Enterprise Wiki

Converging a design can be tricky.  Usually when you push to solve one problem, changes ripple to other parts of your design and inevitably, other issues pop up.  In 2017.3 we are introducing a new feature that may help you solve this problem.  It’s called configurable reporting. 


Partial Reconfiguration involves loading configuration data into an active running design.  While there are some safeguards built into the silicon and bitstreams, such as the Device ID that ensures the correct part is targeted, there are techniques that must be understood and implemented as part of the user’s design.  Designers should follow these recommendations to ensure that partial reconfiguration is done safely and predictably.


Partial Reconfiguration Design Flow – The Configuration Analysis Report

by Xilinx Employee ‎10-13-2017 01:05 PM - edited ‎10-13-2017 02:00 PM (623 Views)

One unique aspect of the Partial Reconfiguration (PR) design flow is that there are multiple versions of the design that must be implemented through place and route.  These different “configurations” have common static design results but differing modules within each Reconfigurable Partition (RP).  Designers must set up timing constraints and floorplans that account for these different modules that will be swapped on the fly.  It can be challenging


How to Constrain Clock Interactions correctly

by Xilinx Employee on ‎09-14-2017 03:27 PM (3,309 Views)

In today's designs it is typical to have a large number of clocks that interact with each other. In order to ensure that Vivado optimizes paths that are critical, it is essential to understand how the clocks interact and how they are related – synchronous and asynchronous clocks.


AXI Interface Debug Using IP Integrator

by Xilinx Employee ‎09-14-2017 03:13 PM - edited ‎09-15-2017 11:21 AM (1,073 Views)

IP Integrator users connect IP blocks to create complex system designs. These block-based designs are typically constructed at the interface level and interfaces usually contain multiple busses and a large number of individual signals. Therefore, in order to easily debug these designs in hardware, it is necessary to verify the design interface-level connectivity.


Support for IP using "Standalone" .dcp Instead of .xci

by Xilinx Employee ‎09-14-2017 11:02 AM - edited ‎09-15-2017 10:56 AM (1,033 Views)

Beginning in 2017.1, we announced that xci and xcix files should be used for all Xilinx IP in our catalog.  This isn’t really new, we’ve actually been communicating that this is our primary recommendation for many years now.  And there are many important reasons for this.  The xci file is an xml file that captures all the configuration settings for the ip and more importantly points Vivado towards the plethora of files that are produced for ip; including - out of context synthesis, constraints, and simulation files.  The xci file is really how Vivado determines if the IP is “fully generated” or if there are any files missing.



Synthesis going Out-of-Date for Unrelated Changes

by Xilinx Employee on ‎06-20-2017 10:53 AM (1,953 Views)

In the project flow, Vivado keeps track of dependencies. As you invoke a particular step, the tool ensures that the previous step is complete


Terminology for IP Flow

by Xilinx Employee on ‎10-26-2016 04:54 PM (2,729 Views)

The Xilinx IP based flow uses terminology that is different from the terms used by typical RTL based designers.

As a result, we need to define certain terminology which might be unique to our IP Flow.

This blog article will attempt to demystify the terminology for flows related to IP.


Managing MicroBlaze Subsystem or DDR Controllers in Update Region of a Tandem with Field Updates Design

by Xilinx Employee ‎05-19-2016 05:39 PM - edited ‎05-19-2016 06:14 PM (3,755 Views)

Adding soft IP Cores such as MicroBlaze Subsystems or DDR Controllers as part of the Update Region of a Tandem with Field Updates Design.


Output Delay

by Xilinx Employee on ‎01-28-2016 01:55 PM (4,955 Views)

In this article, we will discuss the concept behind output_delay.


High Impedance and Out of Context (OOC) Synthesis

by Xilinx Employee on ‎11-05-2015 04:04 PM (4,041 Views)

Vivado allows for a portion of the design to be synthesized Out-Of-Context (OOC).

The basic idea with an OOC flow is that a part of the design is synthesized by itself.


Constraining Asynchronous Clocks

by Xilinx Employee on ‎09-30-2015 02:40 PM (9,175 Views)

For asynchronous clocks, there are four ways to write the constraints.


Time Borrowing in Latches

by Xilinx Employee on ‎08-28-2015 09:28 AM (13,213 Views)

Static Timing Analysis applies a concept called Time Borrowing for latch based designs.

This blog post explains time-borrowing, and is relevant to cases where your design has latches, and your timing report has time-borrowing.


Ensuring Skew Control on Data Lines

by Xilinx Employee on ‎08-02-2015 10:44 PM (4,904 Views)

Sometimes, we might want a few signals to appear at more or less the same time time (i.e. the skew between these signals should not be beyond a certain limit).

A typical situation could be multiple bits of a bus, which should be arriving (almost) together.


Preventing Pulse Filtering in Simulation

by Xilinx Employee on ‎06-04-2015 10:44 AM (7,299 Views)

In general, if your design is passing simulation at a lower frequency but failing at a higher frequency, your first question should be whether the design is “timing clean” at the specified higher frequency.


Why do I get reverse pessimism reduction during CPR?

by Xilinx Employee ‎04-15-2015 11:08 PM - edited ‎04-15-2015 11:20 PM (2,522 Views)

On Chip Variation leads to extreme pessimism in timing analysis.

A portion of this pessimism is recovered through what is called Clock Pessimism Reduction (CPR).

However, we often get queries from users saying that in their designs, instead of recovering a portion of the pessimism, the CPR section is actually doing the opposite, causing them to lose on timing (rather than gaining).


About the blogger...

by Xilinx Employee ‎03-20-2015 03:53 PM - edited ‎05-21-2017 07:39 AM (3,070 Views)

This blog will focus on technical articles explaining how to achieve something specific with XLNX tools and solutions, or explaining some specific aspect of the tool behavior.


About the Author
  • Balachander Krishnamurthy is a Sr. Product Marketing Manager for SDSoC. His responsibilities include product planning, inbound and outbound marketing for Xilinx’s Vivado SDx Design Software. Bala holds a Master's degree in Electrical Engineering from San Jose State University. He has worked at Sun Microsystems and Altera for several years in multiple roles in verification, RTL design, first silicon and board bring-up and as an ASIC Product Manager. He has more than 17 years’ experience in the GPU, CPU, ASIC and FPGA industries. His current focus is FPGA methodology for synthesis, implementation and timing closure.
  • Sanjay is Senior Director, Software Validation, at Xilinx, where he and his team validate the company’s Vivado and SDx tool chains. For more than 20 years, Sanjay has worked in EDA and VLSI in India as well as in Silicon Valley in the United States. He has worked extensively on library characterization and modeling, HDLs (focusing more on Verilog than VHDL), simulation, synthesis, static timing analysis, power, clock domain crossing and synchronization, and rule checker-based verification. Sanjay has been learning Vivado in recent years. He has published three books as co-author and editor: Principles of VLSI RTL Design – A Practical Guide, Constraining Designs for Synthesis and Timing Analysis – Using Synopsys Design Constraints, and Designing with Xilinx FPGAs – Using Vivado. In addition, Sanjay has written numerous articles and papers for trade journals and conferences. He holds three patents related to clock gating and isolation cells. A resident of Hyderabad in India, Sanjay is a graduate of the India Institute of Technology Kharagpur in electronics and electrical communications engineering.