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Visitor opositivo
Visitor
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Registered: ‎02-19-2009

AXI Lite master

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Is it possible to design an IP in Vivado HLS whose top interface is an AXI-Lite master? I found 'axi_master' and 'axi_lite' (which seems to be a slave), but neither 'axi_slave' nor 'axi_lite_master'. 'axi_stream' is the only example that seems to have both master and slave ports.

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Scholar dpaul24
Scholar
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Registered: ‎08-07-2014

Re: AXI Lite master

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@opositivo,

Nonetheless, you might mean that AXI master signals can be connected to an AXI-Lite slave directly, without an intermediate AXI interconnect. If so, please, let me know. I'd be so glad to see a working example.

An axi interconnect would be unnecessary additional logic.

It is easy to connect in VHDL, an full axi_full_master with an axi_lite_slave.

Connect all the compatible signals b/w the slave and the master. Whatever extra signals are remaining with the axi_full_master,

1. Drive all inputs to 0s

2. Keep all outputs unconnected.

Finished!

But this statement  makes me wonder... We have a VHDL2008 IP core with an AXI-Lite slave interface that cannot be simulated in Vivado.

Why?

Has the slave IP been properly built? Was it independently verified?

 

Is it possible to design an IP in Vivado HLS whose top interface is an AXI-Lite master?

Can't comment about HLS, but in calssical RTL design yes. If HLS is limiting you, move to VHDL/Verilog. It is not very difficult to give axi, axi_lite connectivity to ANY IP.

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: AXI Lite master

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No, but the AXI Master will talk to an AXI Lite slave easily. It just automatically drops back to AXI Lite mode.

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Visitor opositivo
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Registered: ‎02-19-2009

Re: AXI Lite master

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Thanks for your reply @u4223374! Unfortunately, I think that the 'automatic drop' is not an option for us. We have a VHDL2008 IP core with an AXI-Lite slave interface that cannot be simulated in Vivado. Now, we want to generate an AXI-Lite master with Vivado HLS in order to connect both IPs together in our own top VHDL file.

Generating an AXI master works ok, as long as the IP is used in a Vivado Block Design, because Vivado will automatically add intermediate AXI interconnects which include additional logic to make the protocol conversion (if needed). Unfortunately, we cannot rely on these AXI interconnects. See the scheme below:

PS (master)      <-> AXI-Lite <-> (slave)  HLS core (master) <-> AXI-Lite <-> (slave) VHDL2008 core
PS [DDR] (slave) <-> AXI Full <-> (master)

So, the HLS core needs three interfaces: AXI Full (master), AXI-Lite (slave) and AXI-Lite (master). We can generate the first two of them, but not the last.

Nonetheless, you might mean that AXI master signals can be connected to an AXI-Lite slave directly, without an intermediate AXI interconnect. If so, please, let me know. I'd be so glad to see a working example.

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Scholar dpaul24
Scholar
461 Views
Registered: ‎08-07-2014

Re: AXI Lite master

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@opositivo,

Nonetheless, you might mean that AXI master signals can be connected to an AXI-Lite slave directly, without an intermediate AXI interconnect. If so, please, let me know. I'd be so glad to see a working example.

An axi interconnect would be unnecessary additional logic.

It is easy to connect in VHDL, an full axi_full_master with an axi_lite_slave.

Connect all the compatible signals b/w the slave and the master. Whatever extra signals are remaining with the axi_full_master,

1. Drive all inputs to 0s

2. Keep all outputs unconnected.

Finished!

But this statement  makes me wonder... We have a VHDL2008 IP core with an AXI-Lite slave interface that cannot be simulated in Vivado.

Why?

Has the slave IP been properly built? Was it independently verified?

 

Is it possible to design an IP in Vivado HLS whose top interface is an AXI-Lite master?

Can't comment about HLS, but in calssical RTL design yes. If HLS is limiting you, move to VHDL/Verilog. It is not very difficult to give axi, axi_lite connectivity to ANY IP.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Visitor opositivo
Visitor
446 Views
Registered: ‎02-19-2009

Re: AXI Lite master

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Thanks a lot @dpaul24! It is awesome to hear that!

An axi interconnect would be unnecessary additional logic.

It is automatically added, tho. I believe that most of the times it is just removed during optimization, but it is hard to know whether it is actually doing anything.

Connect all the compatible signals b/w the slave and the master.

I believed that the HLS core would expect some valid data from some of those ports. But I will definitely give it a try as you say!

But this statement  makes me wonder... (...) Why? Has the slave IP been properly built? Was it independently verified?

AFAIK, Vivado has never supported all the features in VHDL2008, just some of them. Furthermore, support of VHDL has been decaying in the last years. So we use third-party tools for simulation and synthesis.

Can't comment about HLS, but in calssical RTL design yes. If HLS is limiting you, move to VHDL/Verilog. It is not very difficult to give axi, axi_lite connectivity to ANY IP.

All of my designs are VHDL (2008) RTL. I have never used HLS. I'm now trying to guess how to let some colleagues generate IPs with HLS and plug the exported VHDL into the existing VHDL-based workflow with third-party tools. At the end, everything will go back to Vivado as a netlist, which is then implemented to generate the bitstream.

So, as you say, it is not difficult to give AXI connectivity to any IP. Precisely, the examples provided by the IP generator in Vivado are quite useful (although they need quite a lot of manual cleanup). Unfortunately, that's not the use case here.

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Visitor opositivo
Visitor
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Registered: ‎02-19-2009

Re: AXI Lite master

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I now tried it and it works as @dpaul24 and @u4223374 said. I had to 'fix' a couple of things in order to analyse the generated VHDL as VHDL2008, but the result looks good. Thanks!

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Scholar dpaul24
Scholar
354 Views
Registered: ‎08-07-2014

Re: AXI Lite master

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@opositivo,

You are welcome!

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FPGA enthusiast!
All PMs will be ignored
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