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Adventurer
Adventurer
9,482 Views
Registered: ‎12-18-2012

AXI stream driver in HLS custom IP

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Hello,

 

I have made an custom IP in vivado HLS with AXI stream interfaces with the goal of using it besides a MICROBLAZE that would be programmed in the SDK. The driver for programming the ip in SDK is made by HLS and in it I do not see any function concerning the AXI stream interface or the calling of the actual IP finction beside setting start signals...

 

Is this correct or are there driver that are not made correctly by hls...If it is correct how do I send the stream input and receive the stereaming output from the microblaze to the HLS IP? And How do I synchonized this communication with the IP operations?

 

Thanks,

George

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Xilinx Employee
Xilinx Employee
14,242 Views
Registered: ‎08-17-2011

Re: AXI stream driver in HLS custom IP

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adanathel wrote earlier:

I just found a small document stating that there is not support for communication between microblaze and AXI-steam interfaces for IPs made by vivado HLS. There seems to be no support for either stream or memory interfaces. Does not this limit the tool capabilities considerably?


 

 

document referenced:

XAPP745 - Processor Control of Vivado HLS Designs:

"The Vivado HLS tool supports three general categories of signals: streaming interfaces, BRAM
interfaces, and scalar I/O interfaces. From these categories, only the scalar I/O interfaces are
accessible from the processor over the AXI4-Lite interface. Therefore, the automatically
generated IP block APIs from the Vivado HLS tool are only available for IP block status signals
and user-specified scalar I/O ports"

It is fairly old but when i tried it i saw that indeed even in the 2013.2 versions HLS creates API only for the scalar ports...


 

Okay so this still all makes sense to me, I think there is maybe a little misunderstanding here.

 

1- scalar I/O interfaces : go onto AXI4-Lite via directives, processor access through AXI interconnect - direct support as everything is memory / memory mapped ; EDITED, added: and that is supported via the automatically generated APIs (by VHLS).

 

2- BRAM interface: that's the ones generated with ap_memory directive on the arrays, i.e. the ports will look like:

BRAM_PORT_Clk_A,
BRAM_PORT_Rst_A,
BRAM_PORT_EN_A,
BRAM_PORT_WEN_A,
BRAM_PORT_Addr_A,
BRAM_PORT_Dout_A,
BRAM_PORT_Din_A,

this is made to connect to the FPGA BRAM directly (the block RAMs generated via the tools will group the FPGA BRAM into larger blocks) and a processor doesn't have those exact ports so the user needs to use an AXI-BRAM-controller to make it accessible. It then appears from the processor point of view like a "normal" memory space.

 

3- streaming interfaces: XAPP745 focuses on the Zynq and its ARM processors as main example. ARM processors don't have a streaming interface, and here again the user needs a mean to interface with the streams with another IP (refer to me other posts or documents). In the case of the microblaze, then yes there are streaming interfaces options so yes can be used, please also refer to previous posts.

 


 

Interesting that you say that...Because stream outputs are actually present and configurable in the microblaze IP in Vivado IP catalog and are described as fast direct connection from Mc to custom IPs.


 

 

For 3- the pinch of salt to be used here is the definition of "fast": yes AXIS on MB will be faster connection between the MB and IPs than through access via AXI interconnect L that's from the MB point of view.

*but* from the IP point of view you're not going to achieve the best efficiency/throughput because on the other side there is a processor.

 

I hope this clarifies the understanding from everyone.

 

Thanks - Hervé

 

PS Also you can edit your post if if you feel you've quoted the wrong place.

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
7 Replies
Xilinx Employee
Xilinx Employee
9,475 Views
Registered: ‎08-17-2011

Re: AXI stream driver in HLS custom IP

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hello George,

 

This sounds about correct: I don't expect any drivers for AXI4-Stream, however you need to have something in your design that is able to send the data stream in and out of the VHLS created IP.

This is usually done with DMA types IP or AXI streaming fifos.

Checkout XAPP890 - sobel filter : connections to the VHLS IP of figure 6 is what I'd expect.

 

Maybe another question is why do you want to use the stream interfaces?

thanks -

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Adventurer
9,463 Views
Registered: ‎12-18-2012

Re: AXI stream driver in HLS custom IP

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Thanks for the reply i will checki it out.

 

I just found a small document stating that there is not support for communication between microblaze and AXI-steam intefaces for IPs made by vivado HLS. Theere seems to be no support for either stream or memory intefaces. Does not this limit the tool capabilities considerably?

 

I was hoping to use AXI stream for performance reasons as I would expect direct connections to be faster.

I guess I will have to shift to the only other option which would be an ap_hs interface that can be integrated in an typical AXI bus. At least the only option I managed to detect...Unless you might have any other suggestions?

 

Cheers,

George

 

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Xilinx Employee
Xilinx Employee
9,459 Views
Registered: ‎08-17-2011

Re: AXI stream driver in HLS custom IP

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hello George,

 

-> Can you give a reference to this document?

 

The microblaze (MB) has axi-stream (AXIS) interfaces, but I haven't looked into this in anger.

 

In my personal opinion (*happy to learn otherwise), it doesn't make practical sense to have an IP directly attached to the MB via the streams interfaces.

I don't think the MB will be able to sustain the thoughput to do streaming.

At the instructions level if all the data are in MB registers then yes I can think that you can do a few "AXIS_put" and assuming the VHLS IP returns a quick result then the next MB instruction is an "AXIS_get".

 

If you want to stream 1000 values, those values will come from BRAM/DDR so the MB will run a loop: loop while i<SIZE { fetch from RAM, AXIS_put, i++}. this looks fairly inefficient: maybe one AXIS_put every 4-5 instructions and this is moving data (hence DMA / fifos / what ever else etc).

 

As I said, beside the example of a few registers transfer above, I don't see any use cases.

 

Disclaimer: that's my opinion and I haven't try my simple example - if only I had more time!

 

check out xapp890, as I said that's using AXI-streams: what's i'm assuming is happening is something along those lines: setup input memory addresses to be moved, setup output memory addresses to be written, kick-off the VHLS IP. one of the IP will send an interrupt or you can poll something.. everything depends on your setup

 

 

have fun ;-)

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Adventurer
9,451 Views
Registered: ‎12-18-2012

Re: AXI stream driver in HLS custom IP

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The docuiment is this:

 

XAPP745 - Processor Control of Vivado HLS Designs:

 

 

"The Vivado HLS tool supports three general categories of signals: streaming interfaces, BRAM
interfaces, and scalar I/O interfaces. From these categories, only the scalar I/O interfaces are
accessible from the processor over the AXI4-Lite interface. Therefore, the automatically
generated IP block APIs from the Vivado HLS tool are only available for IP block status signals
and user-specified scalar I/O ports"

It is fairly old but when i tried it i saw that indeed even in the 2013.2 verions HLS creates API only for the scalar ports...

 

->The microblaze (MB) has axi-stream (AXIS) interfaces, but I haven't looked into this in anger.

 

Interesting that you say that...Because I stream outputs are actually present and configurable in the microblaze IP in Vivado IP catalog and are described as fast direct connection from Mc to cumstom IPs.

 

I will check the xapp890 and see if i can find a nice solution....

 

Thanks for the reply..

 

 

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Adventurer
Adventurer
9,448 Views
Registered: ‎12-18-2012

Re: AXI stream driver in HLS custom IP

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sorry wrong piece of the post quotes above

 

->The microblaze (MB) has axi-stream (AXIS) interfaces, but I haven't looked into this in anger.

 

->In my personal opinion (*happy to learn otherwise), it doesn't make practical sense to have an IP directly attached to the ->MB via the streams interfaces.

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Xilinx Employee
Xilinx Employee
14,243 Views
Registered: ‎08-17-2011

Re: AXI stream driver in HLS custom IP

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adanathel wrote earlier:

I just found a small document stating that there is not support for communication between microblaze and AXI-steam interfaces for IPs made by vivado HLS. There seems to be no support for either stream or memory interfaces. Does not this limit the tool capabilities considerably?


 

 

document referenced:

XAPP745 - Processor Control of Vivado HLS Designs:

"The Vivado HLS tool supports three general categories of signals: streaming interfaces, BRAM
interfaces, and scalar I/O interfaces. From these categories, only the scalar I/O interfaces are
accessible from the processor over the AXI4-Lite interface. Therefore, the automatically
generated IP block APIs from the Vivado HLS tool are only available for IP block status signals
and user-specified scalar I/O ports"

It is fairly old but when i tried it i saw that indeed even in the 2013.2 versions HLS creates API only for the scalar ports...


 

Okay so this still all makes sense to me, I think there is maybe a little misunderstanding here.

 

1- scalar I/O interfaces : go onto AXI4-Lite via directives, processor access through AXI interconnect - direct support as everything is memory / memory mapped ; EDITED, added: and that is supported via the automatically generated APIs (by VHLS).

 

2- BRAM interface: that's the ones generated with ap_memory directive on the arrays, i.e. the ports will look like:

BRAM_PORT_Clk_A,
BRAM_PORT_Rst_A,
BRAM_PORT_EN_A,
BRAM_PORT_WEN_A,
BRAM_PORT_Addr_A,
BRAM_PORT_Dout_A,
BRAM_PORT_Din_A,

this is made to connect to the FPGA BRAM directly (the block RAMs generated via the tools will group the FPGA BRAM into larger blocks) and a processor doesn't have those exact ports so the user needs to use an AXI-BRAM-controller to make it accessible. It then appears from the processor point of view like a "normal" memory space.

 

3- streaming interfaces: XAPP745 focuses on the Zynq and its ARM processors as main example. ARM processors don't have a streaming interface, and here again the user needs a mean to interface with the streams with another IP (refer to me other posts or documents). In the case of the microblaze, then yes there are streaming interfaces options so yes can be used, please also refer to previous posts.

 


 

Interesting that you say that...Because stream outputs are actually present and configurable in the microblaze IP in Vivado IP catalog and are described as fast direct connection from Mc to custom IPs.


 

 

For 3- the pinch of salt to be used here is the definition of "fast": yes AXIS on MB will be faster connection between the MB and IPs than through access via AXI interconnect L that's from the MB point of view.

*but* from the IP point of view you're not going to achieve the best efficiency/throughput because on the other side there is a processor.

 

I hope this clarifies the understanding from everyone.

 

Thanks - Hervé

 

PS Also you can edit your post if if you feel you've quoted the wrong place.

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
Adventurer
Adventurer
9,439 Views
Registered: ‎12-18-2012

Re: AXI stream driver in HLS custom IP

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Thank you Harve...this clarifies a great deal!

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