10-05-2016 03:55 AM
I have created a "dummy" module to receive AXI4-S input, and output the data part of the stream as an ap_none protocol port.
I don't want to keep the stream interface to the rest of my design, so I'm just trying to single out the data port of the AXI4-S input of the first module and move on. But what happens for example if VALID is '0'? Data would still come to the output, which I don't want since they're invalid.
Can this be done at all? Is what I'm trying to do wrong? Do I have to keep using AXI4-S interfaces for the ins/outs of all my downstream modules?
Thanks in advance!
10-05-2016 07:46 AM
10-05-2016 05:50 AM
What sort of behaviour would you like in that scenario? If you're going from an interface with flow control (ie AXI4-S) to one without flow control, you have to deal with the situation where there's either insufficient data (ie the transmitter isn't ready to send) or too much data (ie the transmitter is sending data but the receiver isn't ready).
In some situations (eg. a fast ADC that's constantly sampling, where you only care about the most recent sample) it doesn't matter much. In others you can guarantee that the transmitter has data available on every single cycle and the receiver can accept data on every single cycle, so it's not a problem - although persuading HLS to give that sort of guarantee can be tricky.
In most situations - where you do actually care about getting all the data and no duplicates - you need to use an interface with flow control. AXI4-S is about the easiest option around. Normally you'd just keep using AXI4-S all the way down the chain.
Incidentally, you can "remove" the flow control on an AXI4-S port in the block diagram, just by expanding the port, tying a constant "1" to the TREADY port, and leaving TVALID disconnected. TDATA is your regular data output. No need for a dedicated block.
10-05-2016 06:17 AM
u4223374 thanks for the reply.
Regarding what behaviour I expect:
My AXI4S input comes from the RX port of an Aurora64b/66b. My understanding was that HLS handles AXI control signals on its own, so for example if my output was also an AXI4S interface, it would "propagate" the input_tvalid signal to the output_tvalid signal (considering that simply output=input). So in that case I wouldn't have to worry about invalid data (again, I might be wrong).
But now that my output port is of an ap_none interface, I don't want invalid data to be forwarded to the rest of my design and considered valid. Since I can't read the input_tvalid signal inside my HLS code, how do I stop or stall any data output, in case my input_tvalid is 0?
10-05-2016 07:46 AM
10-05-2016 08:16 AM
So basically I have to find a way (probably with some kind of flow control) to update the consumer whether he should or shouldn't consider whatever data is currently on the bus.
I'll look into that.