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Participant gicgatv
Participant
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Registered: ‎01-27-2015

Abnormal program termination (11) Vivado HLS 2017.4

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Hi to all,

I have my code in Vivado HLS 2017.4 that was working from simulation up to Export RTL.

I made a data structure change, from 4 Vectors to one vector of struct that contain the 4 vectors as internal fields.

The code is working and running in simulation, but when I launch the C Synthesis, I have the following error:

Abnormal program termination (11)

The console output is following:

 

Starting C synthesis ...
/opt/Xilinx/Vivado/2017.4/bin/vivado_hls /home/gic/Google_Drive/BackgroundSubtractor_HLS/background_subtractor_hls/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'gic' on host 'GATV124' (Linux_x86_64 version 4.4.0-142-generic) on Mon Jul 08 17:51:01 CEST 2019
INFO: [HLS 200-10] On os Ubuntu 16.04.6 LTS
INFO: [HLS 200-10] In directory '/home/gic/Google_Drive/BackgroundSubtractor_HLS'
INFO: [HLS 200-10] Opening project '/home/gic/Google_Drive/BackgroundSubtractor_HLS/background_subtractor_hls'.
INFO: [HLS 200-10] Adding design file 'BackgroundSubtractor_hls.h' to the project
INFO: [HLS 200-10] Adding design file 'BackgroundSubtractor_hls.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'test_BackgroundSubtractor_hls.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/gic/Google_Drive/BackgroundSubtractor_HLS/background_subtractor_hls/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-1'
INFO: [HLS 200-10] Analyzing design file 'BackgroundSubtractor_hls.cpp' ...
WARNING: [HLS 200-40] In file included from BackgroundSubtractor_hls.cpp:15:
./BackgroundSubtractor_hls.h:15:25: warning: extra tokens at end of #ifndef directive [-Wextra-tokens]
#ifndef _BACKGROUND_SUB FPGA_
                        ^
                        //
1 warning generated.
INFO: [HLS 200-10] Validating synthesis directives ...
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'mode_loop3' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_FLATTEN' cannot be applied: Label 'shadow_mode_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_FLATTEN' cannot be applied: Label 'channel_Shadow_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'shadow_mode_loop1' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'PIPELINE' cannot be applied: Label 'shadow_mode_loop1' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'shadow_mode_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'channel_Shadow_loop1' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'channel_Shadow_loop2' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'main_y_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'LOOP_TRIPCOUNT' cannot be applied: Label 'main_x_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'PIPELINE' cannot be applied: Label 'main_x_loop' does not exist in function 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'mean_frame' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'modesUsed_frame' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'variance_frame' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'weight_frame' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'modesUsed_frame_in' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'ARRAY_PARTITION' cannot be applied: Variable 'modesUsed_frame_out' is not declared in 'apply_fpga'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_K0' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_K2' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::cos_K3' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::cos_K1' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_cos_K4' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_cos_K0' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_cos_K0' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_K3' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_K0' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::cos_K0' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'first_order_fixed_16::sin_cos_K1' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::cos_K4' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::cos_K0' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_K2' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_cos_K2' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_K1' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'first_order_fixed_16::sin_cos_K0' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_cos_K3' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::cos_K2' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_K4' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_cos_K1' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_K1' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::cos_K2' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::sin_cos_K2' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'second_order_float::cos_K1' can not be recognized(UNKNOWN VARIABLE) in 'sincos_approximation'.
WARNING: [HLS 200-40] Directive 'RESOURCE' for core 'ROM_1P_LUTRAM' cannot be applied: Variable 'fourth_order_double::sin_cos_K1' can not be recognized(UNKNOWN VARIABLE) in 'sin_or_cos_approximation'.
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 362.398 ; gain = 13.375 ; free physical = 5192 ; free virtual = 25459
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:50 ; elapsed = 00:00:28 . Memory (MB): peak = 362.398 ; gain = 13.375 ; free physical = 5178 ; free virtual = 25456
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-501] Unrolling loop 'Loop-1' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:646) in function 'hls::Mat<16, 480, 0>::write(hls::Scalar<1, unsigned char>)' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:622) in function 'hls::Mat<16, 480, 0>::read()' completely.
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 0>::init' into 'hls::Mat<16, 480, 0>::Mat.1' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:581).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 4096>::init' into 'hls::Mat<16, 480, 4096>::Mat.1' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:581).
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<32, 8, true, (ap_q_mode)5, (ap_o_mode)3, 0>.1' ().
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<57, 33, true, (ap_q_mode)5, (ap_o_mode)3, 0>' ().
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base' ().
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 4, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<33, 9, true, (ap_q_mode)5, (ap_o_mode)3, 0>' ().
INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, unsigned char>.1' into 'hls::AXIGetBitFields<24, unsigned char>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_axi_io.h:71).
INFO: [XFORM 203-603] Inlining function 'hls::AXIGetBitFields<24, unsigned char>' into 'hls::AXIvideo2Mat<24, 16, 480, 4096>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:92).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 4096>::write' into 'hls::Mat<16, 480, 4096>::operator<<' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:662).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 4096>::operator<<' into 'hls::AXIvideo2Mat<24, 16, 480, 4096>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:94).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 4096>::read' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:104).
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<32, 20, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<32, 20, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<32, 18, true, (ap_q_mode)5, (ap_o_mode)3, 0>' ().
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 9, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 9, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<50, 26, true, (ap_q_mode)5, (ap_o_mode)3, 0>' ().
INFO: [XFORM 203-603] Inlining function 'ap_fixed_base<16, 9, true, (ap_q_mode)0, (ap_o_mode)3, 0>::quantization_adjust' into 'ap_fixed_base<16, 9, true, (ap_q_mode)0, (ap_o_mode)3, 0>::ap_fixed_base<32, 13, true, (ap_q_mode)5, (ap_o_mode)3, 0>' ().
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 0>::write' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:424).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 0>::read' into 'hls::Mat<16, 480, 0>::operator>>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:656).
INFO: [XFORM 203-603] Inlining function 'hls::Mat<16, 480, 0>::operator>>' into 'hls::Mat2AXIvideo<8, 16, 480, 0>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:140).
INFO: [XFORM 203-603] Inlining function 'hls::AXISetBitFields<8, unsigned char>.1' into 'hls::AXISetBitFields<8, unsigned char>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_axi_io.h:100).
INFO: [XFORM 203-603] Inlining function 'hls::AXISetBitFields<8, unsigned char>' into 'hls::Mat2AXIvideo<8, 16, 480, 0>' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:143).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 492.297 ; gain = 143.273 ; free physical = 5123 ; free virtual = 25413
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [XFORM 203-602] Inlining function 'std::swap<ap_fixed<16, 4, (ap_q_mode)0, (ap_o_mode)3, 0> >' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:245) automatically.
INFO: [XFORM 203-602] Inlining function 'std::swap<ap_fixed<16, 9, (ap_q_mode)0, (ap_o_mode)3, 0> >' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:246) automatically.
INFO: [XFORM 203-602] Inlining function 'std::swap<ap_fixed<16, 9, (ap_q_mode)0, (ap_o_mode)3, 0> >.1' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:250) automatically.
WARNING: [SYNCHK 200-23] /opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_axi_io.h:49: variable-indexed range selection may cause suboptimal QoR.
INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s).
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:53 ; elapsed = 00:00:31 . Memory (MB): peak = 492.297 ; gain = 143.273 ; free physical = 5097 ; free virtual = 25391
WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'src.data_stream.V' (BackgroundSubtractor_hls.cpp:62).
WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'dst.data_stream.V' (BackgroundSubtractor_hls.cpp:61).
INFO: [XFORM 203-1101] Packing variable 'vectors_window' (BackgroundSubtractor_hls.cpp:20) into a 256-bit variable.
WARNING: [XFORM 203-152] Cannot apply array mapping directives with instance name 'tmp.82': cannot find another array to be merged with.
WARNING: [XFORM 203-152] Cannot apply array mapping directives with instance name 'tmp.2': cannot find another array to be merged with.
WARNING: [XFORM 203-152] Cannot apply array mapping directives with instance name 'tmp.9': cannot find another array to be merged with.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'loop_width' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:73) in function 'hls::AXIvideo2Mat<24, 16, 480, 4096>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'main_loop' (BackgroundSubtractor_hls.cpp:97) in function 'apply_fpga' for pipelining.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 3 for loop 'channel_loop_mean' (BackgroundSubtractor_hls.cpp:208:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 3 for loop 'channel_loop_mean' (BackgroundSubtractor_hls.cpp:208:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 3 for loop 'channel_loop_swap' (BackgroundSubtractor_hls.cpp:249:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 3 for loop 'channel_loop_swap' (BackgroundSubtractor_hls.cpp:249:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 3 for loop 'mode_outer_loop' (BackgroundSubtractor_hls.cpp:121:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 3 for loop 'mode_outer_loop' (BackgroundSubtractor_hls.cpp:121:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 2 for loop 'mode_inner_loop_weight' (BackgroundSubtractor_hls.cpp:292:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 1 for loop 'mode_inner_loop_weight2' (BackgroundSubtractor_hls.cpp:316:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1 for loop 'mode_inner_loop_weight2' (BackgroundSubtractor_hls.cpp:316:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 3 for loop 'channel_inner_loop_mean' (BackgroundSubtractor_hls.cpp:325:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 3 for loop 'channel_inner_loop_mean' (BackgroundSubtractor_hls.cpp:325:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop upper bound from 2 to 3 for loop 'channel_loop' (BackgroundSubtractor_hls.cpp:349:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 3 for loop 'channel_loop' (BackgroundSubtractor_hls.cpp:349:1) in function 'apply_fpga'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 7680 for loop 'main_loop' (BackgroundSubtractor_hls.cpp:98:1) in function 'apply_fpga'.
INFO: [XFORM 203-501] Unrolling loop 'loop_channels' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:91) in function 'hls::AXIvideo2Mat<24, 16, 480, 4096>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-2.1.2' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:646) in function 'hls::AXIvideo2Mat<24, 16, 480, 4096>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:622) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'mode_outer_loop' (BackgroundSubtractor_hls.cpp:120) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'channel_loop_mean' (BackgroundSubtractor_hls.cpp:207) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'mode_inner_loop_swap' (BackgroundSubtractor_hls.cpp:231) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'channel_loop_swap' (BackgroundSubtractor_hls.cpp:248) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'mode_inner_loop_weight' (BackgroundSubtractor_hls.cpp:291) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'mode_inner_loop_weight2' (BackgroundSubtractor_hls.cpp:315) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'channel_inner_loop_mean' (BackgroundSubtractor_hls.cpp:324) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'mode_inner_loop_swap2' (BackgroundSubtractor_hls.cpp:335) in function 'apply_fpga' completely.
INFO: [XFORM 203-501] Unrolling loop 'channel_loop' (BackgroundSubtractor_hls.cpp:348) in function 'apply_fpga' completely.
INFO: [XFORM 203-102] Partitioning array 's.val.assign' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:563) automatically.
INFO: [XFORM 203-102] Partitioning array 'dData.V' (BackgroundSubtractor_hls.cpp:93) automatically.
INFO: [XFORM 203-102] Partitioning array 'mean_backup.V' (BackgroundSubtractor_hls.cpp:190) automatically.
INFO: [XFORM 203-102] Automatically partitioning streamed array 'dst.data_stream.V' (BackgroundSubtractor_hls.cpp:61) .
INFO: [XFORM 203-102] Automatically partitioning streamed array 'src.data_stream.V' (BackgroundSubtractor_hls.cpp:62) .
INFO: [XFORM 203-101] Partitioning array 'pix.val' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:115) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'scl.val' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:615) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'pix.val' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:56) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'data_in.val' (BackgroundSubtractor_hls.cpp:63) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'data_out.val' (BackgroundSubtractor_hls.cpp:64) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'scl.val' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_core.h:615) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'dst.data_stream.V' (BackgroundSubtractor_hls.cpp:61) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'src.data_stream.V' (BackgroundSubtractor_hls.cpp:62) in dimension 1 completely.
INFO: [XFORM 203-602] Inlining function 'std::swap<ap_fixed<16, 4, (ap_q_mode)0, (ap_o_mode)3, 0> >' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:245) automatically.
INFO: [XFORM 203-602] Inlining function 'std::swap<ap_fixed<16, 9, (ap_q_mode)0, (ap_o_mode)3, 0> >' into 'apply_fpga' (BackgroundSubtractor_hls.cpp:246) automatically.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 480 for loop 'loop_width' in function 'hls::AXIvideo2Mat<24, 16, 480, 4096>'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 16 for loop 'loop_height' in function 'hls::AXIvideo2Mat<24, 16, 480, 4096>'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 480 for loop 'loop_width' in function 'hls::Mat2AXIvideo<8, 16, 480, 0>'.
WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 16 for loop 'loop_height' in function 'hls::Mat2AXIvideo<8, 16, 480, 0>'.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (BackgroundSubtractor_hls.cpp:125:76) to (BackgroundSubtractor_hls.cpp:169:52) in function 'apply_fpga'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (BackgroundSubtractor_hls.cpp:133:68) to (BackgroundSubtractor_hls.cpp:169:52) in function 'apply_fpga'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (BackgroundSubtractor_hls.cpp:280:34) to (BackgroundSubtractor_hls.cpp:292:44) in function 'apply_fpga'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (BackgroundSubtractor_hls.cpp:133:68) to (BackgroundSubtractor_hls.cpp:169:52) in function 'apply_fpga'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (BackgroundSubtractor_hls.cpp:304:68) to (BackgroundSubtractor_hls.cpp:306:40) in function 'apply_fpga'... converting 3 basic blocks.
INFO: [XFORM 203-11] Balancing expressions in function 'apply_fpga' (BackgroundSubtractor_hls.cpp:20)...24 expression(s) balanced.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:55 ; elapsed = 00:00:33 . Memory (MB): peak = 554.395 ; gain = 205.371 ; free physical = 5027 ; free virtual = 25336
WARNING: [XFORM 203-631] Renaming function 'hls::Mat2AXIvideo<8, 16, 480, 0>' to 'Mat2AXIvideo' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:125:50)
WARNING: [XFORM 203-631] Renaming function 'hls::AXIvideo2Mat<24, 16, 480, 4096>' to 'AXIvideo2Mat' (/opt/Xilinx/Vivado/2017.4/common/technology/autopilot/hls/hls_video_io.h:49:9)
Stack dump:
0.	Running pass 'CDFG Construction Pass' on module '/home/gic/Google_Drive/BackgroundSubtractor_HLS/background_subtractor_hls/solution1/.autopilot/db/a.o.2.bc'.
Abnormal program termination (11)
Please check '/home/gic/Google_Drive/BackgroundSubtractor_HLS/hs_err_pid7434.log' for details
Finished C synthesis.

Attached the log file. I cannot understand what is happening, Please help.

Many thanks in advance

 

 

 

 

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Accepted Solutions
Participant gicgatv
Participant
100 Views
Registered: ‎01-27-2015

Re: Abnormal program termination (11) Vivado HLS 2017.4

Jump to solution

 

Hi Shreyas,

I have created a small test case that only copy the data I need to process, I will be grateful If you could have a look to understand the Vivado HLS failure.

The test.h is following:

#include "hls_video.h"
#include <ap_fixed.h>
#include <ap_int.h>
#include <stdio.h>
#include <string.h>

// typedef video library core structures
typedef hls::stream <ap_axiu<24,1,1,1> >               AXI_STREAM_IN;
typedef hls::stream <ap_axiu<8,1,1,1> >               AXI_STREAM_OUT;
typedef hls::Mat <MAX_HEIGHT_internal, MAX_WIDTH, HLS_8UC3>     RGB_IMAGE;
typedef hls::Mat <MAX_HEIGHT_internal, MAX_WIDTH, HLS_8UC1>    GREY_IMAGE;
typedef hls::Scalar <3, unsigned char>                 RGB_PIXEL;
typedef hls::Scalar <1, unsigned char>                 grey_PIXEL;
typedef ap_fixed <16,4,AP_RND> 				float_4bits;
typedef ap_fixed <32,20,AP_RND> 			float_20bits;
typedef ap_fixed <16,9,AP_RND> 				 float_9bits;

struct t_data {
	float_9bits mean [9];
    	float_9bits variance [3];
    	float_4bits weight [3];
    	ap_int<16> modesUsed;
    };

// top level function for HW synthesis

void apply_fpga(AXI_STREAM_IN& src_in, AXI_STREAM_OUT& dst_out, t_data *vectors_window, ap_int<4> num_gaussian, ap_int<4> num_channels, ap_int<4> nmixtures, float_4bits 			alphaT,  float_9bits Tb, float_4bits TB, float_4bits Tg, float_9bits varInit, float_9bits varMin, float_9bits varMax, float_4bits prune, float_4bits tau,
					  bool detectShadows, unsigned char shadowVal, ap_int<11> cols, ap_int<11> rows);

 

The Test.cpp is the following:

#include "test.h"


void apply_fpga(AXI_STREAM_IN& src_in, AXI_STREAM_OUT& dst_out, t_data *vectors_window, ap_int<4> num_gaussian, ap_int<4> num_channels, ap_int<4> nmixtures, float_4bits alphaT,  float_9bits Tb,
    				  float_4bits TB, float_4bits Tg, float_9bits varInit, float_9bits varMin, float_9bits varMax, float_4bits prune, float_4bits tau,
					  bool detectShadows, unsigned char shadowVal, ap_int<11> cols, ap_int<11> rows)
        {

	//Create AXI streaming interfaces for the core
	#pragma HLS INTERFACE axis port=src_in bundle=INPUT_STREAM
	#pragma HLS INTERFACE axis port=dst_out bundle=OUTPUT_STREAM
	
        #pragma HLS INTERFACE m_axi port=vectors_window depth=7680 offset=slave bundle=CRTL_BUS 

	#pragma HLS INTERFACE s_axilite port=vectors_window
	
        #pragma HLS INTERFACE s_axilite port=num_gaussian
	#pragma HLS INTERFACE s_axilite port=num_channels
	#pragma HLS INTERFACE s_axilite port=nmixtures
	#pragma HLS INTERFACE s_axilite port=alphaT
	#pragma HLS INTERFACE s_axilite port=Tb
	#pragma HLS INTERFACE s_axilite port=TB
	#pragma HLS INTERFACE s_axilite port=Tg
	#pragma HLS INTERFACE s_axilite port=varInit
	#pragma HLS INTERFACE s_axilite port=varMin
	#pragma HLS INTERFACE s_axilite port=varMax
	#pragma HLS INTERFACE s_axilite port=prune
	#pragma HLS INTERFACE s_axilite port=tau
	#pragma HLS INTERFACE s_axilite port=detectShadows
	#pragma HLS INTERFACE s_axilite port=shadowVal
	#pragma HLS INTERFACE s_axilite port=cols
	#pragma HLS INTERFACE s_axilite port=rows

	#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS

		GREY_IMAGE dst;
		RGB_IMAGE src;
		RGB_PIXEL data_in;
		grey_PIXEL data_out;
		

		t_data vectors_frame_in[7680];
                t_data vectors_frame_out[7680];

	#pragma HLS stream depth=7680 variable=src
	#pragma HLS stream depth=7680 variable=dst

	hls::AXIvideo2Mat(src_in, src);
			
	memcpy(vectors_frame_in,vectors_window,7680*sizeof(t_data);			

    	vectors_Copy_loop2:for( int index = 0; index < 7680; index++ )
    	     {
    	        vectors_frame_out[index] = vectors_frame_in[index];
    	     }

    	image_copy_loop:for( int copy = 0; copy < 7680; copy++)
       	     {
       	        data_in = src.read();
       	        data_out.val[0] =  data_in.val[2];
       	        dst.write(data_out);
       	     }
       	       
       	     memcpy(vectors_window,vectors_frame_out,7680*sizeof(t_data)); 

       	  hls::Mat2AXIvideo(dst, dst_out);

        }

Many thanks in advance!

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4 Replies
Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎07-21-2014

Re: Abnormal program termination (11) Vivado HLS 2017.4

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Hi @gicgatv 

 

I have reproduced the issue at my end.

I will let you know my inputs on the tool failure.

 

Regards,

Shreyas

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Participant gicgatv
Participant
101 Views
Registered: ‎01-27-2015

Re: Abnormal program termination (11) Vivado HLS 2017.4

Jump to solution

 

Hi Shreyas,

I have created a small test case that only copy the data I need to process, I will be grateful If you could have a look to understand the Vivado HLS failure.

The test.h is following:

#include "hls_video.h"
#include <ap_fixed.h>
#include <ap_int.h>
#include <stdio.h>
#include <string.h>

// typedef video library core structures
typedef hls::stream <ap_axiu<24,1,1,1> >               AXI_STREAM_IN;
typedef hls::stream <ap_axiu<8,1,1,1> >               AXI_STREAM_OUT;
typedef hls::Mat <MAX_HEIGHT_internal, MAX_WIDTH, HLS_8UC3>     RGB_IMAGE;
typedef hls::Mat <MAX_HEIGHT_internal, MAX_WIDTH, HLS_8UC1>    GREY_IMAGE;
typedef hls::Scalar <3, unsigned char>                 RGB_PIXEL;
typedef hls::Scalar <1, unsigned char>                 grey_PIXEL;
typedef ap_fixed <16,4,AP_RND> 				float_4bits;
typedef ap_fixed <32,20,AP_RND> 			float_20bits;
typedef ap_fixed <16,9,AP_RND> 				 float_9bits;

struct t_data {
	float_9bits mean [9];
    	float_9bits variance [3];
    	float_4bits weight [3];
    	ap_int<16> modesUsed;
    };

// top level function for HW synthesis

void apply_fpga(AXI_STREAM_IN& src_in, AXI_STREAM_OUT& dst_out, t_data *vectors_window, ap_int<4> num_gaussian, ap_int<4> num_channels, ap_int<4> nmixtures, float_4bits 			alphaT,  float_9bits Tb, float_4bits TB, float_4bits Tg, float_9bits varInit, float_9bits varMin, float_9bits varMax, float_4bits prune, float_4bits tau,
					  bool detectShadows, unsigned char shadowVal, ap_int<11> cols, ap_int<11> rows);

 

The Test.cpp is the following:

#include "test.h"


void apply_fpga(AXI_STREAM_IN& src_in, AXI_STREAM_OUT& dst_out, t_data *vectors_window, ap_int<4> num_gaussian, ap_int<4> num_channels, ap_int<4> nmixtures, float_4bits alphaT,  float_9bits Tb,
    				  float_4bits TB, float_4bits Tg, float_9bits varInit, float_9bits varMin, float_9bits varMax, float_4bits prune, float_4bits tau,
					  bool detectShadows, unsigned char shadowVal, ap_int<11> cols, ap_int<11> rows)
        {

	//Create AXI streaming interfaces for the core
	#pragma HLS INTERFACE axis port=src_in bundle=INPUT_STREAM
	#pragma HLS INTERFACE axis port=dst_out bundle=OUTPUT_STREAM
	
        #pragma HLS INTERFACE m_axi port=vectors_window depth=7680 offset=slave bundle=CRTL_BUS 

	#pragma HLS INTERFACE s_axilite port=vectors_window
	
        #pragma HLS INTERFACE s_axilite port=num_gaussian
	#pragma HLS INTERFACE s_axilite port=num_channels
	#pragma HLS INTERFACE s_axilite port=nmixtures
	#pragma HLS INTERFACE s_axilite port=alphaT
	#pragma HLS INTERFACE s_axilite port=Tb
	#pragma HLS INTERFACE s_axilite port=TB
	#pragma HLS INTERFACE s_axilite port=Tg
	#pragma HLS INTERFACE s_axilite port=varInit
	#pragma HLS INTERFACE s_axilite port=varMin
	#pragma HLS INTERFACE s_axilite port=varMax
	#pragma HLS INTERFACE s_axilite port=prune
	#pragma HLS INTERFACE s_axilite port=tau
	#pragma HLS INTERFACE s_axilite port=detectShadows
	#pragma HLS INTERFACE s_axilite port=shadowVal
	#pragma HLS INTERFACE s_axilite port=cols
	#pragma HLS INTERFACE s_axilite port=rows

	#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS

		GREY_IMAGE dst;
		RGB_IMAGE src;
		RGB_PIXEL data_in;
		grey_PIXEL data_out;
		

		t_data vectors_frame_in[7680];
                t_data vectors_frame_out[7680];

	#pragma HLS stream depth=7680 variable=src
	#pragma HLS stream depth=7680 variable=dst

	hls::AXIvideo2Mat(src_in, src);
			
	memcpy(vectors_frame_in,vectors_window,7680*sizeof(t_data);			

    	vectors_Copy_loop2:for( int index = 0; index < 7680; index++ )
    	     {
    	        vectors_frame_out[index] = vectors_frame_in[index];
    	     }

    	image_copy_loop:for( int copy = 0; copy < 7680; copy++)
       	     {
       	        data_in = src.read();
       	        data_out.val[0] =  data_in.val[2];
       	        dst.write(data_out);
       	     }
       	       
       	     memcpy(vectors_window,vectors_frame_out,7680*sizeof(t_data)); 

       	  hls::Mat2AXIvideo(dst, dst_out);

        }

Many thanks in advance!

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Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎07-21-2014

Re: Abnormal program termination (11) Vivado HLS 2017.4

Jump to solution

Hi @gicgatv 

The issue here seems to be with memcpy function. When input arguments to this function is of type struct having more than one array of elements, tool is crashing.

I have filed CR for this issue and this should be fixed in the next tool release.

Workaround for this is-
1. Add HLS DATA_PACK directive on vector_window- This directive is used for packing all elements of struct into single wide vector.
#pragma HLS DATA_PACK variable=vector_window
2. Use for loop for copying memory files.- as a workaround for ‘memcpy’ function.
for (int i=0; i<7680; i++) {
vectors_frame[i]=vectors_window[i];
}

Hope this will resolve the issue.

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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----------------------------------------------------------------------------------------------
Participant gicgatv
Participant
65 Views
Registered: ‎01-27-2015

Re: Abnormal program termination (11) Vivado HLS 2017.4

Jump to solution

Hi Shreyas!!!

The Workaround not only Synthesized!!! But Also I created bit file in Vivado and  tested on My ZedBoard!!!
It Wooorkksssssss!   Thanks a Billiooonnnn!
 
Best Regards
Giuseppe
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