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Explorer
Explorer
5,484 Views
Registered: ‎08-26-2014

C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

Hello,

 

just wanted to point out that C simulations involving fixed-point word lengths of 32- and 64-bits do not work properly. Either with 31-, 33-, 63- and 65-bits work.

 

I have tried to run them in two Vivado HLS versions: 2015.4 and 2016.1 getting wrong results in both of them. I guess it has to be a bug.

 

Does anyone know if it is solved in later Vivado HLS versions?

 

Thanks,

 

Cerilet

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7 Replies
Scholar u4223374
Scholar
5,456 Views
Registered: ‎04-26-2015

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

Interesting! Could you post a small sample of code that demonstrates the problem? I recently found a sign-extension bug in HLS 2015.2 fixed-point, but that's resolved since 2015.4 (and possibly 2015.3; I didn't test that). It proved resistant to demonstration code; correct HDL was generated whenever I tried to do a simple version of it. In the end I gave up because it's not going to get fixed in old versions anyway.

 

I've also got what is possibly a bug in 2015.4 (and possibly later versions) 1-bit integer handling, but I need to verify that one.

Xilinx Employee
Xilinx Employee
5,441 Views
Registered: ‎05-07-2015

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

HI @cerilet

 

It seems like there are no existing known issues in simulations with fixed point  variables.
Can you please share your test case code,as asked for,  as this can be use case specific also.

Thanks
Bharath
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Explorer
Explorer
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Registered: ‎08-26-2014

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

Hi @nagabhar,

 

They are known indeed. Maybe they did not checked on these two word lengths, but I cannot get good results. Apparently they have been solved in release 2016.2:

http://www.xilinx.com/support/answers/66977.html

 

I do not have time to post the part of the code now. I will try to post it next week.

 

Cheers,

 

Cerilet

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

HI @cerilet

 

I have checked the internal notes of this issue(that corresponds to  66977). Though the AR says it will be fixed in 2016.2.
This has been verified to work fine in 2016.3 HLS onwards. (Note: the problem is only  C simulation gives incorrect value here, RTL co simulation works fine)

your test case will help us see  if even ap_fixed< 32, x>  variables also create trouble during C simulation.

Thanks
Bharath
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Explorer
Explorer
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Registered: ‎08-26-2014

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

Hello again @nagabhar and @u4223374,

 

I just installed Vivado 2106.3 and big surprise: it does the same!

 

Simulation with 31, 33, 63 and 65 bits works perfectly. But this is not the case for 32 and 64 bits.

 

I would prefer to not share my files here. Modifying them before uploading is not a good option for me either because of lack of time.

 

Would be possible to send you the files privately?

 

Thanks,

 

Cerilet

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Explorer
Explorer
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Registered: ‎08-26-2014

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

Hey @nagabhar and @u4223374,

I think I found the problem. I have tried the same code below but changing only the word length and when using 31-bits it gives proper results in both cases. When using 32-bits, the algorithm gives wrong results in the first version of the code. These are the types defined for the case:

typedef ap_fixed<32,2> inout_t;
typedef ap_fixed<32,9> inout_wt_t;


The next code gives me wrong results only when using 32-bits:

isd_temp = isd_1 + (inout_wt_t)Twbase_sigma * (a[0][0] * isd_1 + a[0][1] * isq_1 + a[0][2] * ird_1 + a[0][3] * irq_1 +
    b[0][0] * vsd_1 + b[0][1] * vsq_1 + b[0][2] * vrd_1 + b[0][3] * vrq_1);
isq_temp = isq_1 + (inout_wt_t)Twbase_sigma * (a[1][0] * isd_1 + a[1][1] * isq_1 + a[1][2] * ird_1 + a[1][3] * irq_1 +
    b[1][0] * vsd_1 + b[1][1] * vsq_1 + b[1][2] * vrd_1 + b[1][3] * vrq_1);
ird_temp = ird_1 + (inout_wt_t)Twbase_sigma * (a[2][0] * isd_1 + a[2][1] * isq_1 + a[2][2] * ird_1 + a[2][3] * irq_1 +
    b[2][0] * vsd_1 + b[2][1] * vsq_1 + b[2][2] * vrd_1 + b[2][3] * vrq_1);
irq_temp = irq_1 + (inout_wt_t)Twbase_sigma * (a[3][0] * isd_1 + a[3][1] * isq_1 + a[3][2] * ird_1 + a[3][3] * irq_1 +
    b[3][0] * vsd_1 + b[3][1] * vsq_1 + b[3][2] * vrd_1 + b[3][3] * vrq_1);


The algorithm works in both cases. I just added a casting before multiplying by Twbase_sigma (see in bold what I have changed):

isd_temp = isd_1 + (inout_wt_t)Twbase_sigma * (inout_t)((a[0][0] * isd_1 + a[0][1] * isq_1 + a[0][2] * ird_1 + a[0][3] * irq_1 +
    b[0][0] * vsd_1 + b[0][1] * vsq_1 + b[0][2] * vrd_1 + b[0][3] * vrq_1));
isq_temp = isq_1 + (inout_wt_t)Twbase_sigma * (inout_t)((a[1][0] * isd_1 + a[1][1] * isq_1 + a[1][2] * ird_1 + a[1][3] * irq_1 +
    b[1][0] * vsd_1 + b[1][1] * vsq_1 + b[1][2] * vrd_1 + b[1][3] * vrq_1));
ird_temp = ird_1 + (inout_wt_t)Twbase_sigma * (inout_t)((a[2][0] * isd_1 + a[2][1] * isq_1 + a[2][2] * ird_1 + a[2][3] * irq_1 +
    b[2][0] * vsd_1 + b[2][1] * vsq_1 + b[2][2] * vrd_1 + b[2][3] * vrq_1));
irq_temp = irq_1 + (inout_wt_t)Twbase_sigma * (inout_t)((a[3][0] * isd_1 + a[3][1] * isq_1 + a[3][2] * ird_1 + a[3][3] * irq_1 +
    b[3][0] * vsd_1 + b[3][1] * vsq_1 + b[3][2] * vrd_1 + b[3][3] * vrq_1));


When I use 31-bit, both implementations work. So apparently, when it has to compute very long equations there is some problem with the 32-bit ap_fixed library if you don't do a casting before continuing operating. Limited multiplicator word length? Just guessing.

Thanks again,

Cerilet

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: C simulation in Vivado HLS 2016.1 not working for 32 and 64 bits fixed-point variables

@cerilet

 

I think you're right. I found a similar sort of bug with uint1/ap_uint<1> not long ago. My guess is that for types with width that match standard C/C++ types (ie 64-bit, 32-bit, 16-bit, 8-bit, 1-bit) HLS is designed to just use the existing C types. That way the behaviour of the "HLS" types is absolutely consistent with the equivalent "C" types; a uint32 or ap_uint<32> behaves exactly the same as "unsigned int" or "uint64_t". In my case, an ap_uint<1> perfectly matched the behaviour of a bool, but not the behaviour stated in UG902.

 

Unfortunately, the other widths (eg. 31-bit, 33-bit) do have slightly different behavior - especially in fixed-point where keeping track of which bits are valid after a multiplication is critical. The result is that while the relevant HLS types perfectly match the equivalent C types, they do not match all the other HLS types.

 

 

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