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Visitor srkj990
Visitor
269 Views
Registered: ‎06-13-2019

CODING IN VIVADO HLS DESIGN

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How to assign a particualr bit of input to output in vivado hls design  c/c++ coding

for example :

 out_a[15]=in_a[15]....

out={in_a[5],in_a[4],in_a[3],in_a[2]}

how to write this in hls c coding

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎06-18-2019

回复: CODING IN VIVADO HLS DESIGN

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The C code is vary different with the HDL code.

In the C code, the data or variable must be the multiple of the 8bits.

So if you need do the bit operate, you must use "&" ,“|”,"<<" or ">>" , etc.

for example  

u8 a;

u8 b;

u8 c;

c = ((a & 0x8)|(b & 0x4)>>2);

the result is like "c<= {2'b0,a[3],b[2]};"

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4 Replies
Xilinx Employee
Xilinx Employee
232 Views
Registered: ‎06-18-2019

回复: CODING IN VIVADO HLS DESIGN

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The C code is vary different with the HDL code.

In the C code, the data or variable must be the multiple of the 8bits.

So if you need do the bit operate, you must use "&" ,“|”,"<<" or ">>" , etc.

for example  

u8 a;

u8 b;

u8 c;

c = ((a & 0x8)|(b & 0x4)>>2);

the result is like "c<= {2'b0,a[3],b[2]};"

------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Visitor srkj990
Visitor
183 Views
Registered: ‎06-13-2019

回复: CODING IN VIVADO HLS DESIGN

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Thank you , but if we do like that evertime reamaining bits are becoming zeros ..how to assign the vaslues to the bits without changing the other bits..

here we have module which detects leading one 

module LOD (in_a, out_a);

input [15:0]in_a;

output reg [15:0]out_a;

integer k,j;

reg [15:0]w;

always @(*)

begin

out_a[15]=in_a[15];

w[15]=in_a[15]?0:1;

for (k=14;k>=0;k=k-1)

begin w[k]=in_a[k]?0:w[k+1];

out_a[k]=w[k+1]&in_a[k];

end

end endmodule 

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Xilinx Employee
Xilinx Employee
152 Views
Registered: ‎06-18-2019

回复: CODING IN VIVADO HLS DESIGN

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I think it's a bad way to translate the HDL code to the C code.

You should know what the function want to implement, and coding it by C.

for your example: the result maybe  out = (a & 0x8000) | ((a>>1) & (a & 0x7fff)).

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Visitor srkj990
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139 Views
Registered: ‎06-13-2019

回复: CODING IN VIVADO HLS DESIGN

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Thank you for your reply ....

I am writing a code and i got struck in this module what actually i want is 

if 16'b0010_0101_1110_1111 is given as input the output has to be  16'b0010_0000_0000_0000

I got stuck here ....

 

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