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Visitor tony_obrien
Visitor
5,492 Views
Registered: ‎09-23-2016

Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi,

 

I get the following error when trying to generate a .bit file for an example design using the 10/25G Ethernet IP core.

 

  • [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: DUT/inst/i_xxv_ethernet_4_top_0/i_xxv_ethernet_4_CORE (xxv_ethernet_4_xxv_ethernet_v1_3_0_mac_baser_axis_hsec_cores)

 

I have looked at previous Answer records which recommend resetting and Regenerating output products. This hasn't worked for me. And my license is correct.

What I cannot understand is: I have a project that contains the Eth core and that will complete correctly already. However my example design project that contains the same core will not generate a bit file.

I am using Vivado 2016.2.

 

Any help would be greatly appreciated.

Thanks

 

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Visitor tony_obrien
Visitor
9,836 Views
Registered: ‎09-23-2016

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @vijayak

 

I regenerated the example from scratch and now it is working correctly.

Thank you for your help.

 

Tony

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6 Replies
Xilinx Employee
Xilinx Employee
5,475 Views
Registered: ‎10-24-2013

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @tony_obrien

 

Can you please attach the license manager screenshot that shows your IP license?

Thanks,Vijay
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Visitor tony_obrien
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5,470 Views
Registered: ‎09-23-2016

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi Vijay,

Is this what you require?

 

 

LicMgr.png

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Moderator
Moderator
5,450 Views
Registered: ‎07-01-2015

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @tony_obrien,

 

It can happen if you have only design linking license.

Please share the output xinfo.txt of below Tcl command:

report_environment -file xinfo.txt

Thanks,
Arpan
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Visitor tony_obrien
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5,403 Views
Registered: ‎09-23-2016

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @arpansur,

The file is attached. However, I'm not sure if this is the problem. I am able to generate a .bit file with another project that also contains the same core.

 

Regards

Tony

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Xilinx Employee
Xilinx Employee
5,349 Views
Registered: ‎10-24-2013

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @tony_obrien

Looks like you have valid license.

1) Can you try removing the IP from the project and add it again?

2) Also try creating a IP example design and see if you are able to get through.

 

Thanks,Vijay
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Visitor tony_obrien
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9,837 Views
Registered: ‎09-23-2016

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @vijayak

 

I regenerated the example from scratch and now it is working correctly.

Thank you for your help.

 

Tony

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