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Visitor kalte
Visitor
5,947 Views
Registered: ‎05-22-2012

Corrupt design.xml file after System Generator export from Vivado HLS

Hi,

first of all, Vivado HLS is magic, congratulations.

 

I was playing around for a while. Coding in C++, doing high-level synthesis, exporting to System Generator ISE and implementing on a Kintex device. It has actually worked already last week. However, after some extensions and modifications the generated .xml File for the System Generator Block seems to be corrupt (\solution1\impl\sysgen\design.xml). After loading the export into the System Generator "Vivado HLS" block, the GUI says "...is not a valid AnyTable file". The xml file seems not to be generated completely, although I do not get any error during the Vivado HLS export.

 

These are the last lines in the file:

...

],
  'DesignConstraint' => {
      'clk_period' => '8.000000'
  },
  'library' => 'VIVADO_HLS',
  'model' => {
    'modelParameters'=>{
        'combinational' => '0',
        'latency' => '1',
        'II' => 'x'
    },
    'ports' => [

 

No idea what to do. By the way, It makes no difference, if I export for System Generator ISE or Vivado. The vhdl files seems ok.

 

I work with Vivado HLS 2013.2

Thanks

Heiko

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2 Replies
Visitor kalte
Visitor
5,932 Views
Registered: ‎05-22-2012

Re: Corrupt design.xml file after System Generator export from Vivado HLS

I have been commenting out an internal subfunction call, than the System Generator export (.xml) file was generated correctly and importing to the Vivado HLS block worked. Afterwards I put the function call back in and it still worked. I have no idea why, but at the moment I seem to have no problems. If if find out the reasen I will post it.

Regards

Heiko

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Xilinx Employee
Xilinx Employee
5,930 Views
Registered: ‎08-17-2011

Re: Corrupt design.xml file after System Generator export from Vivado HLS

hello Heiko,

maybe you project was corrupted..? or there's a tiny change somewhere that made it all work!
- Hervé

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