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Observer h.hamil
Observer
204 Views
Registered: ‎05-25-2019

Detect falling edges to generate impulsions

Hi,

Using Vivado_HLS I’m trying to generate impulsions (signal_out) of same amplitude and width at every falling edge of signal_in.

 

this is the code for the detection of falling edges of signal_in:

//==============================

if (((*signal_in)==1) && (*signal_in ==0)) 

{

*signal_out <= '0';

*signal_out <= '1';

*signal_out <= '0';

}

//===============================

The simulation result (shown by wave viewer) is attached bellow.

Could anyone provide helpful suggestions?

 

 

q1.JPG
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2 Replies
Voyager
Voyager
168 Views
Registered: ‎03-28-2016

Re: Detect falling edges to generate impulsions

@h.hamil,

The first step of an HLS design is to create C/C++ code that performs the user's alogrithm.  There is no way that your if statement ("if (((*signal_in)==1) && (*signal_in ==0))") will ever be true.  "Signal_in" can not be both "1" and "0" at the same moment in time.  This will not work in Verilog/VHDL either.

Edge detection requires comparing a signal at two different points in time.  That requires the design to hold on to old values to compare against the new.  In RTL, that would be a register.  There are a couple of ways to do it in HLS depending upon your design methodology.

If you are using a Frame based method you would need something like:

for(i=0;i<N;i++) {
    if(signal_in[N]==1 && signal_prev==0) {
        signal_out[N] = 1;
    }
    else {
        signal_out[N] = 0;
    }
    signal_prev = signal_in[N];
}

If you are using a Sample based method then you would need something like:

static data_t signal_prev;
if(signal_in==1 && signal_prev==0) {
    signal_out = 1;
}
else {
    signal_out = 0;
}
signal_prev = signal_in;

I would recommend looking at the following HLS User Guides:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug902-vivado-high-level-synthesis.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug1270-vivado-hls-opt-methodology-guide.pdf

https://www.xilinx.com/support/documentation/sw_manuals/ug1197-vivado-high-level-productivity.pdf

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Observer h.hamil
Observer
119 Views
Registered: ‎05-25-2019

Re: Detect falling edges to generate impulsions

Hello tedbooth,

I tried the following code and here is no error when running C simulation + C synthesis but,  unfortunately i did not get the signal_out which still zero.

Any more idea? Thanks

============================

static data_t signal_prev;
if(signal_in==0 && signal_prev==1) {
    signal_out = 1;
}
else {
    signal_out = 0;
}
signal_prev = signal_in;

=============================

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