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Visitor chesh
Visitor
3,419 Views
Registered: ‎01-17-2016

Enable interrupt in testbench

Hi,

 

I would like to see the behavior of the interrupt with respect to the Stream output of my HLS block.

Is it possible to enable the interrupt of the HLS node in the testbench?

 

Then I would like to do a C/RTL CoSimulation and enable the dumptrace.

This will generate a static simulation file (wdb) which I can open in Vivado so I can analyze the behaviour of all signals.

 

Thanks,

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