01-10-2013 08:15 AM
I need tweek manually the vhdl RTL descriptions made by HLS.
I tried to create a new project and use the generated vhdl files as source. My problem is that vivado cannot seem to be able to use the HLS core library files that are used for the components generated. So I used the VHDL descriptions generated by the export RTL option in HLS situated in <project>/solution<#>/impl.
There the component names in the VHDL files for the previously genereted modules using the HLS library are changed. But the files for the alternative component descriptions are nowhere to be found and I cannot impelement the design.
It is sth that I am missing or is it that it is impossible to use the HLS generated VHDL in vivado unless it is packadged in an IP block?
01-10-2013 10:03 AM
You can use HLS generated vhdl file in vivado. Ther is no such restrictions.
if you are getting any error message then please post the error message.
01-11-2013 01:32 AM
Thanks for the reply...
These are the errors I get from using the RTL descriptins found in the syn folder:
[Synth 8-2947] error reading binary file 'c:/xilinx/14.2/ise_ds/planahead/scripts/rt/data/vhdl/vdbs/ieee_proposed/fixed_float_types.vdb'
[Synth 8-522] parsing error: error in use clause. package 'fixed_float_types' in the libraray 'ieee_proposed' not found. Make sure the package reference and source library in this file is correct and the package declaration is added to the project and compiled to the proper library. ["C:/Users/xxxx/Documents/vivado_prj/IOCELL/IOCELL.srcs/sources_1/imports/ieee_FP_pkg/fixed_pkg_c.vhd":23]
[Synth 8-1031] fixed_round_style_type is not declared ["C:/Users/Turin/Documents/vivado_prj/IOCELL/IOCELL.srcs/sources_1/imports/ieee_FP_pkg/fixed_pkg_c.vhd":28]
If I use the RTL descriptions of the impl folder, the same components that came from the same library have different names and their description are nowhere to be found...
01-11-2013 05:54 AM
Please review some steps:
1. click on export rtl.
2. go for "Pcore for EDk".
3.This will create one implementation folder in side your project directory.
use this file to make a project in ISE or in vivado.
let me know the outcome
01-11-2013 07:16 AM
I only have the system generator and IP-XACT options for RTL export....
I believe that is because I have the HLS license and not the HLS_vivado license that supports older than virtex 7 devices and using EDK would be useful...I have requested for an updated license but it takes some time for the request to get through...
01-11-2013 07:52 AM
I partially got it actually....
As I said before using the RTL descriptions coming from the export RTL process the components giving the library error were replace with others but i could not find their descriptions in the folder...
These files were actually on a different folder in impl/ip/hdl/ip
Now I am missing one instantiation:
[Designutils 20-1022] Could not resolve non-primitive black box cell 'floating_point_v6_1' instantiated in module 'U0'.
01-14-2013 03:00 AM
I am still trying to use the vhld files from HLS in vivado but for every new vhdl I add that is needed in the design there is always an other missing and not being the same folder files.
Is this really the proccesdure to use the RTL description in vivado. Take the vhld files generated and add the extra vhd files for the inner components from 4-5 different folders?Is there not a more automatic way to be done?
01-14-2013 06:03 AM
Review some steps that i have follow to reproduce the same issue at my end .
1.open one sc_sequ_thread ran C systhesis as well as simulation.
2. click on export rtl and select the ip-xact option. this create a impl folder inside the project directory.
3.create the new project in vivado with the vhdl.
(vhdl file present inside this project directory sc_sequ_cthread\proj_sc_sequ_cthread\solution1\impl\ip\hdl\vhdl)
it properly synthesize.
Please review above steps and conform that you are following the same steps.
and using the vhdl which are present in this directory ...\impl\ip\hdl\vhdl.....
also let me know if you still facing any issue.
01-14-2013 07:08 AM
I did that...There still I have the same problem with the missing sources...It does synthesize of course but using the missing modules as black boxes which then cannot be implemented..(let alone that the synth report is propably false since modules are missing).
01-14-2013 07:11 AM
i want to have a look at your project file .is it possible for you to upload the file at forum.?
01-15-2013 12:47 AM
You want just the project file(.xrp) or the whole project?I cannot upload anything that includes code...
01-15-2013 09:49 AM
please upload the vivado_hls complete project. or you can also make small test case and show me the error message.
01-16-2013 03:02 AM
I am not allowed to upload the my project...but I can upload an example project that I have the same prioblems when i used its VHDL files in Vivado....(see http://www.sendspace.com/file/p9p3zq the attachment was too large for the forum)
Here if I make a vivado project and adding the sources taken from the solution1/impl/ip/hld/vhdl folder (from the HLS project ) it also asks for that files in the solution1/impl/ip/hld/ip folder. If I add them there are still missing files(I think it is actually just one in this case)...It does synthezise but with the missing files as black boxes and the implemetation fails.
I have found the missing files on the solution1/impl/ip/tmp.srcs folder but they also have missing files for their internal modules...
01-16-2013 08:50 AM
i am not able to download the design files form this site.
so i would suggest you to please upload the header file,design file and test bench file in forum
01-25-2013 02:08 AM