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Explorer
Explorer
102 Views
Registered: ‎05-23-2017

Estimated clock period (2.533ns) exceeds the target

Though I tried the solution: https://www.xilinx.com/support/answers/53118.html

But it still complains about this issue:

How could I get ride of this issue?

INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'read_query_or'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'read_query_or0'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
WARNING: [SCHED 204-21] Estimated clock period (2.533ns) exceeds the target (target clock period: 3.33333ns, clock uncertainty: 0.9ns, effective delay budget: 2.43333ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
    'mul' operation ('mul1', /home/SDAccel_Examples_2018_2/getting_started/host/PCAF_FPGA_sub_v2s2sub40/src/pcaf_fpga.cpp:248) (2.53 ns)

 

 

 void read_query_or(const D_point_512 *query_or, Dtype_s *query_or_oc_0){//,Dtype_s *query_or_oc_1, Dtype_s *query_or_oc_2){
D_point_512 query_or_temp;
#pragma HLS ARRAY_PARTITION variable = query_or_temp.x complete dim=0

Dtype_s query_or_oc_temp[D_OR]; #pragma HLS ARRAY_PARTITION variable = query_or_oc_temp complete dim=0 ap_uint<10> loop_num = D_OR/16;// each 512 bit including 16 float data read_query_or0:for(ap_uint<10> j=0; j<loop_num; j++){ #pragma HLS PIPELINE query_or_temp=query_or[j]; ap_uint<10> ind1=j<<4; //the Critical pathread_query_or1: for(ap_uint<10> k=0; k<16; k++){ ap_uint<10> ind2=ind1+k; //query_or_oc_0[j*16+k] = query_or_temp.x[k];//f_temp; query_or_oc_0[ind2] = query_or_temp.x[k];//f_temp; } } }

 

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2 Replies
Scholar u4223374
Scholar
57 Views
Registered: ‎04-26-2015

Re: Estimated clock period (2.533ns) exceeds the target

Since it's easily faster than the required performance, I'd either (a) ignore it, or (b) turn down the uncertainty to something like 0.5ns.

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Observer p27803
Observer
41 Views
Registered: ‎03-31-2017

Re: Estimated clock period (2.533ns) exceeds the target

I would also suggest exporting the RTL and running through synthesis and place and route.  The clock period estimate from HLS is just that - an estimate. P&R will give you the real numbers (of course you will also need to run P&R with your full design once your HLS is complete).

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