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Newbie jrausche
Newbie
7,599 Views
Registered: ‎12-22-2015

FFT in Pipelined Streaming I/O with no Cyclic Prefix Insertion Mode

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Hi,

 

I would like to implement a realtime 4k FFT, but could not get an II=4096 realized. The solution below produces an II=12429.

Is there a way to get this done?

 

Best Regards,

Juergen

 

struct config1 : hls::ip_fft::params_t {
    static const unsigned ordering_opt = hls::ip_fft::bit_reversed_order;
    static const unsigned max_nfft = FFT_NFFT_MAX;
    static const bool hast_nfft = false;
    static const bool ovflo = false;
    static const unsigned arch_opt =  hls::ip_fft::pipelined_streaming_io;
    static const unsigned complex_mult_type = hls::ip_fft::use_mults_resources;
    static const unsigned stages_block_ram = 5;
    static const unsigned phase_factor_width = FFT_PHASE_FACTOR_WIDTH;
    static const unsigned butterfly_type =  hls::ip_fft::use_xtremedsp_slices;
};




[...]





void fft_4k(complex<float> fft_in[4096],complex<float> fft_out[4096])
{
#pragma HLS dataflow

 bool dir = true;
 bool ovflow[1];


 config_t fft_config;
 status_t fft_status;

 fft_config.setDir(dir);
 fft_config.setSch(0x2AB);

 // FFT IP
 hls::fft<config1>(fft_in, fft_out, &fft_status, &fft_config);

}

 

 

1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
13,865 Views
Registered: ‎03-24-2010

Re: FFT in Pipelined Streaming I/O with no Cyclic Prefix Insertion Mode

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Check 

http://www.xilinx.com/support/answers/59678.html

Regards,
brucey
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3 Replies
Xilinx Employee
Xilinx Employee
13,866 Views
Registered: ‎03-24-2010

Re: FFT in Pipelined Streaming I/O with no Cyclic Prefix Insertion Mode

Jump to solution

Check 

http://www.xilinx.com/support/answers/59678.html

Regards,
brucey
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Newbie jrausche
Newbie
7,062 Views
Registered: ‎12-22-2015

Re: FFT in Pipelined Streaming I/O with no Cyclic Prefix Insertion Mode

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Thank you for the feedback. I have already tried:

 

cosim_design -setup -rtl vhdl -tool modelsim
export_design -evaluate vhdl -format ip_catalog

 

But I also get the same II in the waveform as shown in the Vivado HLS report.

 

Regards,

Juergen

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Newbie jrausche
Newbie
7,054 Views
Registered: ‎12-22-2015

Re: FFT in Pipelined Streaming I/O with no Cyclic Prefix Insertion Mode

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By forcing the right signal to '1' in Questasim I have managed to identify an II of 4097.

 

Best Regards,

Juergen

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