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12,104 Views
Registered: ‎05-22-2012

HLS IP Customization parameters

Hi,

Is it possible to add to HLS IP some customization parameters? I mean i have some software defines:

e.g. #define F_SIZE 6000, and i wan't to customize it (before synthesis) in Vivado -> Customize block option.

 

Thank You.

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17 Replies
Moderator
Moderator
12,093 Views
Registered: ‎04-17-2011

Re: HLS IP Customization parameters

That wont be possible from HLS. You can do this in the Packaged IP once you add it in Vivado IP Catalog.
Regards,
Debraj
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Participant chertio
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11,963 Views
Registered: ‎03-04-2008

Re: HLS IP Customization parameters

Hi Debrajr,

 

I think the question is how to insert a placeholder in the C code used for HLS, so the parameters can be propagated in from the IP package tool? Is that possible?

 

Thank you

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Moderator
Moderator
11,941 Views
Registered: ‎04-17-2011

Re: HLS IP Customization parameters

That is what I was mentioning. It cannot be propagated from HLS directly. Once you have packaged the IP, you can use the Customize Parameters option and add Custom Parameter to your IP which can be visible once you add the IP in Block Design/Vivado. Refer to page 33 of the document: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug1118-vivado-creating-packaging-custom-ip.pdf
Regards,
Debraj
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Visitor jtani
Visitor
11,546 Views
Registered: ‎06-21-2011

Re: HLS IP Customization parameters

I try to get this running too.

In order to add customization parameters, I think VIVADO HLS have to generate generics.

 

Document UG1118 does not describe how to generate VHDL-generics form "#define statements in HLS code".

It only describes, how to import them.

 

Can you help?

Is there an example?

 

Regards,

jtani

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Xilinx Employee
Xilinx Employee
11,535 Views
Registered: ‎08-17-2011

Re: HLS IP Customization parameters

hello all -

 

it's not possible to have defines that will modify the IP that VHLS generates.

In the flow, VHLS generates the IP first, then this is used in Vivado / Vivado IPI. This IP is totally defined at compile time.

 

If you allowed parameters then you would need to regenerate the whole IP - eg you have a parameter that makes a code use char or int -> the tool needs to rerun to reapply the scheduling , timing estimatation, pipelineing, datapath growth etc. to have a parameter that changes a FIFO depth: the whole thing needs to change the state machine etc.

Anything that you think you want to have parameterized outside needs to be pulled outside of the VHLS IP. then configure like Debraj explained or use other IPs..

 

I hope this clears things out.

- Hervé

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Contributor
Contributor
6,920 Views
Registered: ‎03-19-2015

Re: HLS IP Customization parameters

So in a very trivial situation when I return the input, for example:

entity my_nop is
    generic (
        data_width : integer := 32
    );
    port (
        A : in std_logic_vector(data_width-1 downto 0);
        B : out std_logic_vector(data_width-1 downto 0);
    );
end my_nop;
architecture Behavioral of my_nop is
    B <= some_edit_to_data(A);
end Behavioral;

Is this something HLS can't do?

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Xilinx Employee
Xilinx Employee
6,910 Views
Registered: ‎08-17-2011

Re: HLS IP Customization parameters

Hi @mkarwat

 

your response / question is not relevant to the original issue and topic.

 

VHLS can take an input and generate a new (output) value from it.. what would be the point of designs with no inputs??!! please start a new thread..

- Hervé

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Contributor
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6,905 Views
Registered: ‎03-19-2015

Re: HLS IP Customization parameters

Ok, I gues I could be a bit more specific. This topic is about creating a parameter for an IP designed in HLS, and that is what I wanted to ask about. I understand that I can't "have a parameter that makes a code use char or int". But what about a parameter that changes the width of the data? Like generic in the example I provided.

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Xilinx Employee
Xilinx Employee
6,900 Views
Registered: ‎08-17-2011

Re: HLS IP Customization parameters

HI @mkarwat,

 

Similar answer as before: not possible.

If you want an IP with different data_width, then just do that.. a design with 512 or 1 might be widely different.

If you have to have only one then create one with 512 bits and instantiate with 1 bits input and outputs but i give no guarantees that the later tools will do the correct trimming for you.

Assuming the tool is able to tie off the unused inputs, are you ready to live with an IP that is potentially 512 times too big?

 

The tool might be improved in the future to support some flavor of the initial request/topic but I plainly don't know.

 

I hope this helps

- Hervé

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Explorer
Explorer
6,239 Views
Registered: ‎07-13-2015

Re: HLS IP Customization parameters

@herver

 

Is there any chance of Xilinx telling us how the Video Test Pattern Generator block works? It's apparently built in HLS, but there are some handy customization options in Vivado (data width, maximum rows/columns, etc). Was it just built in HLS originally and then extensively hand-crafted to achieve that result, or is there hidden functionality in HLS that can do this?

 

Cheers,

Evan

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Teacher muzaffer
Teacher
6,223 Views
Registered: ‎03-31-2012

Re: HLS IP Customization parameters

@evanslatyer VTPG comes in encrypted C code and it gets synthesized by HLS after it is configured. So there is no magic. You change some #defines and redo HLS.
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Visitor jtani
Visitor
6,217 Views
Registered: ‎06-21-2011

Re: HLS IP Customization parameters

Hi @all,
actually I am using #defines for e.g. different bit-width and redo HLS.
In order to do this, I have to open the HLS-project, change the #define, compile the project and export it to the repository.
In vivado I have to refresh the IP repository and update my IP.

 

I agree with evanslatyer. The VTPG has customization options in VIVADO! This is great.

re-customize IP.PNG

 

My questions:
1. HOW are this options passed to HLS?
2. After an option was changed:
- How will the HLS-project compiled?
- Do I have to open the HLS-Project? Sorry, I am not able to try it. I have no license for this IP. And I did not found a further configurable HLS-IP in VIVADO:

 

Regards,
Andreas

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Teacher muzaffer
Teacher
6,211 Views
Registered: ‎03-31-2012

Re: HLS IP Customization parameters

most of this is undocumented so I am not sure how well you can approximate what Xilinx is doing but at a high level this is how it works; the tool which ties everything together is TCL.
* the dialog box for the IP is described by v_tpg_v7_0.tcl
* the file v_tpg_config.ttcl (when is it called?) retrieves the parameters set by clicking OK on the config dialog and generates a file called tph_config.h
* hls_commands.ttcl generates the hls command script
* s_axis_video.xit does some other magic (who knows what?)
* finally one calls the "compile_c" Vivado command to convert the C/C++ files (presumably tpg_config.h is #included by v_tpg.cpp) to HDL using HLS and generate the IP.
* also there is a misc/logo.png file which has the vivado HLS icon in it. Presumably one can make an IP with a different file and it would be used in the IP package.

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: HLS IP Customization parameters

to answer your questions specifically:
>> 1) HOW are this options passed to HLS?

through a config.h file which is generated by BD configuration process.

>> - How will the HLS-project compiled?

vivado has a compile_c command similar to synth_design

>> Do I have to open the HLS-Project?

No, you just have/generate the files necessary in a directory and point compile_c to them.
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Visitor jtani
Visitor
6,159 Views
Registered: ‎06-21-2011

Re: HLS IP Customization parameters

This is very interesting.

Is there perhaps an example anywhere?

As I said, I don't have a license for this IP.

Are there any other HLS-IPs delivered with the VIVADO standard intallation?

 

What a pity, that xilinx do not provide a complete documentation for this stuff. :-(

 

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Explorer
Explorer
6,158 Views
Registered: ‎07-13-2015

Re: HLS IP Customization parameters

@muzaffer

 

I know it's not magic, but it'd be really nice if we could do a block the same way!

 

At the moment the flow is "put block into Vivado, note that the bus width isn't suitable for this application, open HLS, change the #define, re-run synthesis, export the IP, refresh the IP repository in Vivado, insert the new IP, set the address, run synthesis" (optional: "note that the new block still has the same name as the old block and is therefore causing conflicts, open HLS, change the top function name, re-run HLS, export the IP, etc").

 

Whereas with the VTPG you just change the bus width and everything else works instantly.

 

I may have to try it using the steps you outlined, but it feels like the sort of thing that could/should be a really simple GUI or directive in HLS. Just like you can make global variables accessible on the external interfaces, an option to make #defines available in Vivado would do very nicely.

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: HLS IP Customization parameters

@jtani just copy the v_tpg_7 directory to a local repo and add it to the repo list.
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