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Explorer
Explorer
362 Views
Registered: ‎05-23-2011

How doese HLS handle wraparounds during aritmetic operations?

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Hi

I implementet an IIR BiQuad filter in HLS for a collegue.
The transfer function represents a bandpass.
The inputs have the type of ap_int<13>. The coefficents are from the type of ap_fixed<32,2> to handle values from -2 up to +2.
The outputs and some internal registers have the type of ap_fixed<32,13>.

The calculation is:

output =  coeff1 * input
            + coeff2 * register1
            + coeff3 * register2
             - coeff4 * register3
             - coeff5 * register4

I am not sure if HLS automatically handles the internal overflows correctly.
This can depend on the sequenze HLS is making the calculations.

Can enybody give my some hinds, if i hade to do something to avoid problems during the calculations?

kind regards

Thomas

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1 Solution

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Xilinx Employee
Xilinx Employee
342 Views
Registered: ‎01-09-2008

Re: How doese HLS handle wraparounds during aritmetic operations?

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Vivado HLS always performs internal computations with full precision and applies Rounding/Saturation (specified in 'output' type definition) when assigning the value to 'output'
==================================
Olivier Trémois
XILINX EMEA DSP Specialist
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4 Replies
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎01-09-2008

Re: How doese HLS handle wraparounds during aritmetic operations?

Jump to solution
Vivado HLS always performs internal computations with full precision and applies Rounding/Saturation (specified in 'output' type definition) when assigning the value to 'output'
==================================
Olivier Trémois
XILINX EMEA DSP Specialist
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Explorer
Explorer
316 Views
Registered: ‎05-23-2011

Re: How doese HLS handle wraparounds during aritmetic operations?

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Hi

Is your answer true for all HLS versions?
I´m still using 2016.3.

I took a look into the .vhdl Code and I found somthing strange.
Multiplier which have smaler outputs than the sum of the both inputs:

    iir_biquad_mul_32eOg_U2 : component iir_biquad_mul_32eOg
    generic map (
        ID => 1,
        NUM_STAGE => 6,
        din0_WIDTH => 32,
        din1_WIDTH => 32,
        dout_WIDTH => 62)

    iir_biquad_mul_30dEe_U1 : component iir_biquad_mul_30dEe
    generic map (
        ID => 1,
        NUM_STAGE => 3,
        din0_WIDTH => 30,
        din1_WIDTH => 15,
        dout_WIDTH => 43)

And some additions of 62 bit vectors into other 62 bit vectors.
So no vector extensions during the calculations.

Kind regards
Thomas

 

 

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Xilinx Employee
Xilinx Employee
308 Views
Registered: ‎01-09-2008

Re: How doese HLS handle wraparounds during aritmetic operations?

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Hi Thomas,

 

if the coefficients are constant, VHLS takes this into account:

 

0.3*x1 + 0.4*x2 --> the complete precision result is the datatype (x) extended to the right with the precision of the coefficients. There is no need to touch the integer part as the sum of the coefficients is less than 1.

 

==================================
Olivier Trémois
XILINX EMEA DSP Specialist
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Explorer
Explorer
304 Views
Registered: ‎05-23-2011

Re: How doese HLS handle wraparounds during aritmetic operations?

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Hi

The coefficients for the IIR came from external. So there is no optimasation possible.

But I had some multiplikations with sin(x) and cos(x) and this coefficients have the same type like the coefficients of the IIR filter.
This can be the reasion for the width of the multiplikationresult.

Kind regards
Thomas

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