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Observer stefanoribes
Observer
2,664 Views
Registered: ‎07-25-2016

How to Simulate an OpenCL NDRange in Vivado HLS

Hi everyone,

I'm developing OpenCL kernels in Vivado HLS. Most of them can be executed within an NDRange, so the proper work-group coordinates can be setup accordingly. In details, I can achieve so when I run my design on the FPGA, i.e. when I set the registers of the AXI-interface of the kernel:

 

-- 0x10 : Data signal of group_id_x
--        bit 31~0 - group_id_x[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of group_id_y
--        bit 31~0 - group_id_y[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of group_id_z
--        bit 31~0 - group_id_z[31:0] (Read/Write)
-- 0x24 : reserved

In this way I'm able to check the correctness of my synthesized kernels when I launch large NDRanges.

However, the process of synthesizing and implementing the entire design (to be run onto the FPGA) takes time.

 

So to check the kernels correctness I know that there's the function hls_run_kernel (found on UG902):

 void  hls_run_kernel(
 	const char *KernelName, 
 	ScalarType0 *Arg0, int size0, 
 	ScalarType1 *Arg1, int size1, ...)

But its documentation is very poor and I wasn't able to find any example on launching/testing an NDRange in Vivado HLS.

 

Can anyone provide me some examples or a way to set the work-group coordinates while running a testbench in Vivado HLS?

 

Thank you in advance,

 

Stefano

 

(I attached a very simple kernel I would like to test, just to give an idea)

 

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