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Visitor dravik
Visitor
120 Views
Registered: ‎06-20-2019

How to deal with a 'static' configuration

Hi all,

I am experimenting with HLS for the last few weeks. I manage to create pretty satifying results compared to VHDL. One 1 thing I still not getting succesfull.

I want to use a configuration that can be updated from a CPU. My application has X number of different configurations with the same layout, different values. I created an typedef for that. Idealy the settings are stored in LUTRAMS.

This configuration can be updated some now and then, but most runs it will probably remain the same. The most simple example I could think of would be to just return the settings to an output port based on an input selector.. For my example it will return one out of 7 configurations. For me the latency and iteration time of updating the configuration does not matter, but I want to be able to read the settings with an latency of 0 clocks.

void settings_top(uint6 settings_selector, Settings settings_in[7], Settings *settings_out){
#pragma HLS DATA_PACK variable=settings_in
#pragma HLS RESOURCE variable=settings_in core=RAM_2P_LUTRAM
#pragma HLS INTERFACE s_axilite port=settings_in

*settings_out = settings_in[settings_selector];
}

This takes and iteration and latency of 8 clocks. Does anyone have a suggestion on how to configure your HLS block with a static configuration over a axi bus, without affecting your normal iteration time?

 

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4 Replies
Visitor sinill57
Visitor
109 Views
Registered: ‎07-09-2018

Re: How to deal with a 'static' configuration

Hi @dravik

 

I think you shouldn't choose the parameters inside the FPGA. A much easier way is to choose between the configurations in the CPU and then send the selected  config to the IP core.

Then, your function would look like this:

void top(Settings settings_in, /* other ports here */ )

{

#pragma HLS INTERFACE s_axilite port=settings_in

#pragma HLS INTERFACE ap_stable port=settings_in

 

/* and then you just use the fileds of settings_in */

}

 

This way, the parameter changes would not affect you main algorithm in any way

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Advisor xilinxacct
Advisor
106 Views
Registered: ‎10-23-2018

Re: How to deal with a 'static' configuration

@dravik 

Can you share your 'Settings' typedef to see how much data you are trying to move? (In a simple typedef with a few simple scalars, I would expect 1 latency at default clock target of 10) What is your target clock (and device)?

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Visitor dravik
Visitor
89 Views
Registered: ‎06-20-2019

Re: How to deal with a 'static' configuration

Thanks for the quick replies.

My settings are similar to:

typedef struct Settings {
uint1024 value0;
uint1024 value1;
uint1024 value2;
uint1024 value3;
uint32 value4;
} Settings;

Keeping the data in FF is not desired.

Clock is about 3ns, Virtex UltraScale+ FPGAs family.
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Advisor xilinxacct
Advisor
70 Views
Registered: ‎10-23-2018

Re: How to deal with a 'static' configuration

@dravik 

Ahh... yes, your structure is not simple scalars... I think under the hood it is generating a loop to process those ap variables. In a small test, I saw that if I try to transfers an array, it creates multiple cycles, but if I did simple scalars, it can all happen in one cycle, as it can be done in parallel. I don't know if your code can/should be factored that way, but if it can, you may go faster.

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)

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